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Synopsys, July 27, 2022

AI-Driven Verification: Saving Time with Verdi Regression Debug Automation

Analyzing the thousands of failures from daily regression runs is a manual, tedious, and error-prone process. The process can significantly impact quality-of-results, time-to-results and cost-of-results. The Synopsys Verdi® Regression Debug Automation (RDA) is an artificial… AI-Driven Verification: Saving Time with Verdi Regression Debug Automation

DAC 2022

Design Automation Conference, 2022

The Design Automation Conference (DAC) is recognized as the premier event for the design and design automation of electronic chips to systems.  DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers,… Design Automation Conference, 2022

DVCon Europe, December 6-7, 2022

DVCon Europe 2022

The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier European technical conference on system, software, design, verification, validation or integration. It is a place where the latest methodologies and technologies for… DVCon Europe 2022

Mirabilis, March 10, 2022

Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)

• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it… Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)

Andes, Feb 15, 2022

Optimized Chip Design with Main Processors and AI Accelerators

Presented by Paul Karazuba, VP of Marketing, Expedera & John Min, Director of Field Application Engineering, Andes Technology About this talk As AI capability is beginning large-scale deployment into edge devices, many wonder about the… Optimized Chip Design with Main Processors and AI Accelerators

Synopsys, February 2, 2022

ASIP Virtual Seminar 2022

Extending RISC Processors into Flexible Accelerators using ASIP Designer Case Studies in Artificial Intelligence and Image Signal Processing The slow-down of Moore’s law and Dennard scaling has triggered an increased awareness of application-specific instruction-set processors… ASIP Virtual Seminar 2022

Mirabilis

Compare Performance-power of Arm Cortex vs RISC-V for AI applications

In the Webinar, we will show you how to construct, simulate, analyze, validate, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of… Compare Performance-power of Arm Cortex vs RISC-V for AI applications