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Compare Performance-power of Arm Cortex vs RISC-V for AI applications
October 21, 2021 @ 9:00 am - 10:00 am PDT
In the Webinar, we will show you how to construct, simulate, analyze, validate, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53/A77/A65AE/N1, SiFive u74, and other vendor cores. Aside from the processor resources such as cache and memory, the system will contain custom switches, Ingress/Egress buffers, credit flow control, DMA AI accelerators, NoC and AMBA AXI buses. The evaluation and optimization criteria will be task latency, dCache hit-ratio, power consumed/task and memory bandwidth. The parameters to be modified are bus topology, cache size, processor clock speed, custom arbiters, task thread allocation and changing the processor pipeline.
1. Validating architecture models using mathematical calculus and hardware traces
2. Construct custom policies, arbitrations and configure processor cores
3. Select the right combination of statistics to detect bottlenecks and optimize the architecture
4. Identify the right use of stochastic, transaction, cycle-accurate and traces to construct the model
Alex Su is a FPGA solution architect at E-Elements Technology, Hsinchu, Taiwan. Prior to that, Mr Su has worked at ARM Ltd for 5 years in technical support of Arm CPU and System IP.
Deepak Shankar is the Founder of Mirabilis Design and has been involved in the architecture exploration of over 250 SoC and processors. Deepak has published over 50 articles and presented at over 30 conferences in EDA, semiconductors, and embedded computing. This webinar is in partnership with SemiWIki.com and Mirabillis.