This DVClub will consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to design verification. Agenda (GMT): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction –… DVClub Europe – AI/ML in Verification
This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM Agenda (GMT) 13:00 Welcome and Introduction – Mike Bartley, Tessolve 13:00 Epsen Tallaksen, EmLogic – Get the right FPGA quality through efficient… DVClub Europe: Latest VHDL Verification Techniques
Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster, to interconnect to die-to-die. Agenda (BST) 12:00 Welcome and Introduction – Mike Bartley, Tessolve 12:00 Nick Heaton, Cadence Design Systems –… DVClub Europe – Performance Testing and Analysis
Best Conference Papers from 2022 These papers are selected from DVCon and CadenceLive! in 2022 as being most relevant to the DVClub Europe community. Agenda (GMT) 12:00 Welcome and Introduction – Mike Bartley, Tessolve 12:00 Lukas… DVClub Europe – Best Conference Papers from 2022
With the popularity of the RISC-V open architecture, many companies are looking for Verification Strategies for developing their own cores or how to verify their integration into a subsystem or SoC. Time Session Description Slides… RISC-V Verification Strategies
