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DVClub Europe – Performance Testing and Analysis
April 25 @ 12:00 pm - 1:30 pm BST
Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster, to interconnect to die-to-die.
12:00 Welcome and Introduction – Mike Bartley, Tessolve
12:00 Nick Heaton, Cadence Design Systems – SoC Verification in a Multi-chip, Multi-die world
For additional information please visit the Tessolve DVClub Europe page for this event.
DVClub Europe is made possible through the generous support of our sponsors: Agnisys Inc , ARM, Breker Verification Systems, Cadence, Imperas Software, OneSpin Solutions, Siemens, ST Microelectronics and Synopsys.
Tessolve reserves the right to cancel registration at its discretion.