DVClub Europe – Performance Testing and Analysis

Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster, to interconnect to die-to-die.

Agenda (BST)

12:00 Welcome and Introduction – Mike Bartley, Tessolve

12:00 Nick Heaton, Cadence Design Systems – SoC Verification in a Multi-chip, Multi-die world

12:30 TBD

13:00 TBD

13:30 Close

Additional Information

For additional information please visit the Tessolve DVClub Europe page for this event.

Sponsors

DVClub Europe is made possible through the generous support of our sponsors: Agnisys Inc , ARM, Breker Verification Systems, Cadence, Imperas Software, OneSpin Solutions, Siemens, ST Microelectronics and Synopsys.

Tessolve reserves the right to cancel registration at its discretion.