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RISC-V Verification Strategies

November 29 @ 12:00 pm - 1:30 pm GMT

DVClub Europe 2022

With the popularity of the RISC-V open architecture, many companies are looking for Verification Strategies for developing their own cores or how to verify their integration into a subsystem or SoC.

Time Session Description Slides Videos
12.00 GMT Welcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
12.05 GMT RISC-V processor verification with new open standard RVVI based methodology
Simon Davidmann, Imperas Software
12.25 GMT RISC-V Verif Generators : A Configurable ISA warrants a Configurable Verification Environment
Dr. Neel Gala, InCore Semiconductors Pvt. Ltd.
12.45 GMT RISC-V SoC integration verification including system coherency. Is your RISC-V SoC-ready?
John Sotiropoulos, Breker Verification Systems Inc
13.05 GMT CORE-V-VERIF: an open-source SV/UVM environment for RISC-V cores
Mike Thompson, OpenHW Group
13.25 GMT Closing Remarks
13.30 GMT Close

About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.

Details

Date:
November 29
Time:
12:00 pm - 1:30 pm GMT
Event Categories:
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Website:
Event Website

Organizer

Tessolve
View Organizer Website

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