Jasper Beefs Up Formal Verification
I talked with Holly Stump at Jasper by phone last week about their newest release of formal verification tools. Holly has worked before at Sequence and Precedence. Because formal tools examine the state space of…
I talked with Holly Stump at Jasper by phone last week about their newest release of formal verification tools. Holly has worked before at Sequence and Precedence. Because formal tools examine the state space of…
ChipEstimate.com has archived all of the IP presentations in PDF from DAC called IP Talks. Companies include: Algotronix ARM Cadence CAST CebaTech Common Platform Denali Dolphin Elliptic eSilicon Impinj IPextreme KiloPass Mixel MoSys PLDA Rambus TakeCharge Sidense Synopsys…
David Heller taped 64 brief videos at DAC this month, ranging from 48 seconds to well over 4 minutes. His guest speakers all work at EDA companies that exhibited at DAC, from start-up Analog Rails to giant…
Sunday evening EDAC did something different by trying to entertain the DAC audience with a game show, well it was novel yet I predict a show that will not be repeated. In years gone by…
I’m a SPICE and transistor-level IC guy so will make the rounds on Monday to see: Nascentric (OmegaSim – FastSPICE) Berkeley DA (Analog FastSPICE) Synopsys (HSIM, NanoSim – FastSPICE) Mentor (AdIT – FastSPICE) Cadence (UltraSim…
Cadence dominates the custom IC layout market and CiraNova gets a lot of attention about automating analog layout, but I’m here to tell you about an interesting company called Micro Magic that is offering a free IC layout viewer called MAX-View.…
This special offer is to encourage you to invite friends and colleagues to register with DAC for a Free Exhibit Pass. This promotion includes complementary admission to the Exhibit Floor, Exhibitor Forum, Turing Award and…