As electronic systems continue to become more complex and integrate greater functionality, SoC developers are faced with the challenge of developing more powerful, yet more energy-efficient devices. The processors used in these applications must be… Synopsys Processor IP Summit 2024: RISC-V, DSP and NPU IP for Your Diverse SoC Processing Needs
The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain, often starting from a baseline such as the… Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
Finite Impulse Response (FIR) filters are widely used in communication, consumer electronics, and many other digital signal process (DSP) applications. A FIR filter includes a complex pipelined datapath based on arithmetic functions such as multipliers… Formal Validation of a Datapath Pipelined Design with VC Formal
The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/LiDAR – requires SoCs to have an optimal balance of DSP performance and low power/area. In… DSP IP for High Performance Sensor Fusion on an Embedded Budget
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it… Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)