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efabless, November 30, 2023

Latest Innovations and Updates in ASICs with Efabless

In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. Topics Include: OpenFrame – a… Latest Innovations and Updates in ASICs with Efabless

efabless, November 16, 2023

Latest Innovations and Updates in ASICs

In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. Topics Include: – OpenFrame –… Latest Innovations and Updates in ASICs

efabless, august 17, 2023

Using Generative AI for ASIC Design

Tools like ChatGPT can be used for a variety of purposes, including writing Verilog. Unfortunately, these models are not (yet) perfect, and the quality of the output varies heavily depending on how you use them.… Using Generative AI for ASIC Design

OSDA 2023

3rd Workshop on Open-Source Design Automation

Call for papers There is no doubt that proprietary EDA tools are successful, mature, and fundamental for hardware development. However, the “walled garden” approach created by closed-source tool flows can hamper novel FPGA/ASIC-based applications and… 3rd Workshop on Open-Source Design Automation