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RISC-V

Mirabilis, April 18, 2024

Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP

Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP

Mirabilis, 18 April 2024

Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP

Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP

Andes, January 25, 2024

Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series

Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered… Read More »Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series

Andes, November 14, 2023

Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips

As semiconductor industry leaders, Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors, join us for an insightful… Read More »Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips