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June 11 @ 9:00 am - 5:00 pm PDT

Andes, June 11, 2024

Recently, RISC-V, with its open, streamlined, and scalable configuration, has become the mainstream solution adopted by leading market players, paving the way for widespread technological innovation. In the RISC-V application field, there has been rapid development in forward-looking areas such as automotive electronics and AI. The development application processors has attracted a lot of attention, and the need for product information security has also increased.

As a Premier member and a leading brand in 32/64-bit embedded CPU cores, Andes, a member of RISC-V International, will host an annual seminar on June 11 at the DoubleTree by Hilton San Jose. The theme of the seminar is “ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends.” The event aims to introduce the market dynamics and development trends of RISC-V, discuss Andes’ comprehensive product portfolio recently launched, and assist industries in fully utilizing the high-performance/low-power characteristics of the RISC-V architecture to enhance product competitiveness and move towards a future full of opportunities.

The seminar will feature presentations and on-site demonstrations by numerous RISC-V ecosystem partners, providing insights into the latest international trends and technological developments in RISC-V. Let us join hands to celebrate this event and explore the potential of RISC-V together with industry experts, paving the way for a diverse application vision!

Here is our event schedule

09:00 – 09:25 Registration
09:25 – 09:30 Opening-Market Watch, Frankwell Lin, Chairman & CEO, Andes Technology
09:30 – 09:50 Customer Use Case Presentation
09:50 – 10:25 Unlocking RISC-V’s potential on Intelligence Application Processing, Dr. Charlie Su, President & CTO, Andes Technology
10:25 – 10:45 Safe and Secure Software Solutions for Andes RISC-V, Robert Redfield, Director of Business Development, Green Hills Software
Green Hills Software and Andes Technology offer combined capabilities for the AndeStar™ V5 Architecture, enabling the efficient development and confident deployment of RISC-V-based designs in systems with critical requirements for functional safety and security. Green Hills Software’s offering features real-time operating systems, powerful compilers and advanced C/C++ development tools that leverage the company’s 40-years of microprocessor experience.

10:45 – 11:05 Lauterbach Debug and Trace of Andes RISC-V Processors, Dennis Griffiths, Field Applications Engineer, Lauterbach
Lauterbach, the leader in RISC-V debug and trace, will be discussing and demonstrating the TRACE32 tools for the Andes N27 on the Big Orca reference hardware.Using our TRACE32® tools you can debug and control any RISC-V core (along with all of the other cores) in any SoC via a single debug interface, all at the same time. TRACE32® tools support real-time on- and off-chip tracing for all major RISC-V trace systems.

11:05 – 11:35 Break
11:35 – 11:55 Customer Use Case Presentation
11:55 – 12:15 Ecosystem Partners Showcase – Siemens EDA
12:15 – 13:15 Lunch
13:15 – 14:05 RISC-V Ecosystem Panel: Open-Source is Transforming AI and Hardware
Moderator: Dylan Patel, Chief Analyst, SemiAnalysis
Panelist: Charlie Cheng, CEO, Cucina, Inc.
Please stay tuned for the mystery guest
Please stay tuned for the mystery guest
Please stay tuned for the mystery guest
Please stay tuned for the mystery guest
14:05 – 14:35 Driving Safe and Secure Innovations with Andes RISC-V Solutions, Andes Technology
14:35 – 15:05 Break
15:05 – 15:25 Synopsys Solutions Empower Software Development on Andes Processors, Larry Lapides, Business Development Director, Synopsys
Andes processor IP is increasingly being used in high performance applications such as AI/ML, and in use cases where there are reliability, safety and security requirements. For these and other advanced applications software development is critical. Starting software development early, before RTL is ready, can accelerate software tasks by months. Other key pieces of the software task include hardware-software co-verification, building prototypes and enabling CI/CD software methodology in production. Synopsys tools, including ImperasFPM fast processor models of the Andes cores, Virtualizer for virtual prototypes, and the HAPS and ZeBu hardware-assisted verification tools, have been supporting and enabling Andes customers for more than 5 years. This talk will discuss software methodology in general, and provide case studies of Andes-Synopsys joint customers.

15:25 – 15:45 Are you a professional developer? Then why use amateur tools? Shawn Prestridge, US FAE Manager, IAR
What can professional tools bring to a professional developer? Many features that optimize your time, such as live instruction tracing, complex and conditional breakpoint types, functional safety certification, comprehensive live technical support, and much more. The optional code analysis tools can also help you quickly spot code issues while you are desk-checking your code to make your code fast and accurate. This session will quickly cover the benefits that each of these features brings in terms of time (and ultimately, money) savings. Your time isn’t free – optimize it by using tools commensurate with your talent that allow you to deliver your product to market as quickly as possible!

5:45 – 16:35 RISC-V Ecosystem Panel: Unlocking the RISC-V Application Processor Potential
The Application Processor market presents a tens-of-billions annual value opportunity, which expands by an order of magnitude at the device scope, and is similarly scaled, if not more, at the software application level. The target segments are diverse, ranging from consumer electronics and industrial computing to automotive, networking, and communications. The incumbent compute ISAs for application processors are either Arm or x86, but RISC-V has emerged as a fast-evolving and maturing alternative, gaining strong traction across the value chain. This growth is fueled by the advent of AI, whose support is becoming ubiquitous across all compute platforms, with RISC-V offering significant value for AI computing. Initiatives like defining and ratifying an iterative set of extensions for the RISC-V application (RVA) profile have established a standard architecture base, enabling hardware and software vendors to develop interoperable solutions. Efforts by organizations like RISE and major Linux-based and Android-based operating system providers have accelerated the software-based infrastructure support for RISC-V. Despite these advancements, challenges remain in areas such as ecosystem maturity, hardware performance and availability, software compatibility, and general public perception. This panel discussion will delve into these exciting topics to explore the opportunities, the progress made, and how to overcome these challenges to unlock the potential of RISC-V application processors.

Moderator: Mark Himelstein, Heavenstone, Inc.
Panelist: Dr. Charlie Su, President & CTO, Andes Technology
Lars Bergstrom, Director of Engineering, Android team, Google
Barna Ibrahim, Vice-Chair, RISE
Dr. Sandro Pinto, Co-founder, OSYX Technologies
16:35 – 17:00 Lucky Draw & Evening Reception


June 11
9:00 am - 5:00 pm PDT
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Andes Technology
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The DoubleTree by Hilton
2050 Gateway Place
San Jose, CA United States
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