Chiplets are emerging as a new way of building IC systems via heterogeneous integration, and Universal Chip Interconnect Express (UCIe) is one of the standards… Read More »UCIe PHY Modeling and Simulation with XMODEL
I found the first holiday video from Ansys posted on December 14th, so enjoy the photos and videos to bring you some cheer as 2022… Read More »Merry Christmas 2022
Learn how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable… Read More »Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
It’s time for my annual Christmas and Holiday greetings from Semiconductor, #SemiEDA and #SemiIP companies. Send me your favorites. Past years: 2020 2019 2018 2017 2016 Happy holidays… Read More »Merry Christmas 2021
When verifying large SoC designs, one needs to write SystemVerilog models for analog/mixed-signal blocks to comply with the digital verification flow, such as UVM. This… Read More »Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example