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Keysight, February 28, 2024

Keysight EDA Connect World Tour: Santa Clara – High Speed Digital

Shift Left with the Modern Design Center Artificial intelligence (AI) is redefining high-speed digital designs. Your ability to design, simulate, and test — using an automated, integrated workflow — is what will set you apart.… Keysight EDA Connect World Tour: Santa Clara – High Speed Digital

Cadence, February 8, 2024

Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis

Signal and power integrity (SI/PI) are top priorities for engineers designing today’s high-speed, high-density PCBs. Easy-to-use in-design analysis directly integrated into the Allegro PCB design environment uncovers SI/PI issues early in the design process, leading… Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis

Siemens, January 16, 2024

PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture

“Right first time” is a goal we all aspire to, but how often does it really happen? Even when we follow layout rules as closely as possible, problems creep into the layout that cause issues… PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture

Synopsys, December 13, 2023

CMOS Circuit Techniques for Wireline Transmitters Part III

Synopsys Webinar – Part III In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge… CMOS Circuit Techniques for Wireline Transmitters Part III

Synopsys, November 29, 2023

CMOS Circuit Techniques for Wireline Transmitters Part II

Synopsys Webinar – Part II In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge… CMOS Circuit Techniques for Wireline Transmitters Part II

Synopsys, November 8, 2023

CMOS Circuit Techniques for Wireline Transmitters Part I

Synopsys Webinar – Part I  In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge… CMOS Circuit Techniques for Wireline Transmitters Part I

Synopsys, July 18, 2023

Key MAC Considerations for the Road to 1.6T Ethernet Success

224G SerDes designs are a reality and the path to 1.6T is clearer than ever. This webinar delves into the considerations, challenges and solutions designers need to know for the MAC required for these 224G Ethernet… Key MAC Considerations for the Road to 1.6T Ethernet Success