Skip to content
Loading Events

« All Events

  • This event has passed.

CMOS Circuit Techniques for Wireline Transmitters Part II

November 29, 2023 @ 10:00 am - 11:00 am PST

Synopsys, November 29, 2023

Synopsys Webinar – Part II

In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G, which is now enabled by 112G Ethernet as the interconnect of choice, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps.

Part I: Wednesday, November 8, 2023

  • Motivation for SERDES
  • Transmitter Requirements
  • Current/Voltage Mode Drivers

Part II: Wednesday, November 29, 2023

  • High Order Multiplexers
  • FFE Equalization
  • DSP-DAC Based TX Architectures
  • 1-UI Pulse Generation Circuits

Part III: Wednesday, December 13, 2023

  • Output Matching Network
  • Measurements and Simulation Techniques


Listed below is the industry leader scheduled to speak.

Noman Hai

Manager, Analog & Mixed-Signal Circuit Design
Synopsys, Inc.

Noman Hai received the B.E. degree from NED University, Karachi, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University, Sweden in 2006 and the Ph.D. degree from University of Waterloo, Canada, in 2012. He has worked at Philips Semiconductors, MACOM, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits, design methodology and automation, and mixed-signal circuits. He holds three U.S. patents.


November 29, 2023
10:00 am - 11:00 am PST
Event Categories:
Event Tags:
Event Website


View Organizer Website

Leave a Reply

Your email address will not be published. Required fields are marked *