The 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024) are being held at Kolkata, India, during January 6-10, 2024. VLSID 2024 is returning to the city after 8 years… VLSID 2024
Previous years: 2022 2021 2020 2019 2018 2017 2016 The @AgileAnalog team would like to send Season’s Greetings to all our customers and partners across the globe. It has been another busy year and we look forward to delivering more of… Happy Hanukkah, Merry Christmas – 2023
Dear SIPI Engineer, As a member of the engineering community, you are invited to attend Synopsys Signal & Power Integrity Special Interest Group event taking place at Hilton Santa Clara. This event is conveniently located… Signal & Power Integrity Special Interest Group
Webinar Overview: This webinar explores debugging SystemC code with basic tools, including issues and strategies to make improvements. A large portion of the webinar includes a demonstration of a small design. Topics include single-stepping without… Debugging SystemC with GDB
Synopsys Webinar – Part III In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge… CMOS Circuit Techniques for Wireline Transmitters Part III
A worldwide connected Event !! IP-SoC 2023 will be the 26th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. The event is the annual opportunity for IP… IP-SoC Conference 23 – Grenoble
System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding design-for-test… Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation
Synopsys Webinar – Part II In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge… CMOS Circuit Techniques for Wireline Transmitters Part II
IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints… Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
