A worldwide connected Event !!
IP-SoC 2023 will be the 26th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems.
The event is the annual opportunity for IP providers and IP consumers to share information about technology trends, innovative IP SoC products, Breaking IP/SoC News, Market evolution and more.
The Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives, market analyzer and technical experts from Foundry/technology, to new applications share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business.
As far as the application domains are concerned it is important to give high to new application domains and take into account new system requirements such as 3D packaging, Security, Artificial Intelligence, Green Electronics, …
And over all you cannot miss The wine Tasting Party !!
Exhibition tables and “discussion panels” will favor vendor and customer meetings.
Any question? Please contact us
Registration and Exhibition installation opens at 7 am.
- Day 1 – December 4th, 2023
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9.00 am
Introduction Session |
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Welcome : Innovation in semi conductor industry
Gabrièle Saucier
CEO
D&R
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Empowering Innovation in the Age of Custom Silicon
Eric Lalardie
Director
Arm Ltd.
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9.40 am
Break |
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10.00 am
New technology the lead of innovation
Chairperson: Yves Quere – CEA
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Greening the Road Ahead: Revolutionizing the Automotive Industry with FD SOI Technology
Philippe Flatresse
Product Marketing
SOITEC
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Technologies enabling future mobile connectivity & sensing
Francois Brunier
Partnership Program Manager
SOITEC
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Digital Beamforming design in mmW: A 22nm FDSOI transceiver practical case
Jérôme Prouvée
Layout Engineer & Project Manager
CEA
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11.00 am
Break |
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11.20 am
Artificial Intelligence IP and SoC
Chairperson: Costas Conistis – Alphawave Semi
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Meeting the Needs of AI Training with HBM3
Philip Van Den Heuvel
Regional Sales Manager
Rambus, Inc.
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Innovative Integrated IP SoC Design for Edge AI
Tim Menasveta
Director of IoT Product Management
Arm Ltd.
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Transforming Far-Edge Computer Vision with Energy-Efficient A
Vincent Huard
Chief Technology Officer
Dolphin Design
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12.30 pm
Lunch |
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1.30 pm
New Challenges
Chairperson: Eric Lalardie – Arm
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The Lossless Compression Challenge: from Networking to Data centers
Dr. Calliope-Louisa Sotiropoulou
Sales Engineer
CAST, Inc.
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Addressing connectivity scalability in the AI world with Mulit-Standard IO Chiplets driving next generation interconnects
Michael Klempa
Product Marking Specialist
Alphawave Semi
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2.10 pm
Break |
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2.30 pm
Safety Critical Applications
Chairperson: Dr. Calliope-Louisa Sotiropoulou – CAST
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IP Core Considerations for Ensuring Functional Safety in Safety-Critical Applications
Philipp Jacobsohn
Senior Staff Applications Engineer
SmartDV Technologies
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GRLIB: VHDL IP library for fault-tolerant SoC
Fabio Malatesta
Product Marketing Engineer
Frontgrade Gaisler
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3.10 pm
Automotive Applications |
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CAN XL – can safety go in hand with performance?
Jacek Hanke
CEO
Digital Core Design
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Solve the Latest ISO 21434 Cybersecurity Challenge with an Automotive HSM
Ruud Derwig
Senior Staff Engineer for Security IP
Synopsys, Inc.
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4.00 pm
Break |
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4.20 pm
Security Solutions
Chairperson: Bart Stevens – Rambus, Inc.
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Which IP for Which Security Certification Standard,
Ludovic Merrien
Security Certification Leader
Tiempo Secure
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LDPC Encoder/Decoder
Manish Mahajan
Founder
Secantec, Inc.
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Security from chip to cloud with PQC (Post-Quantum Cryptography)
Brice Gaignoux
EMEA Pre-Sales Engineer
Secure-IC
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5.20 pm
Break |
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5.40 pm
Security Solutions – 2
Chairperson: Ruud Derwig – Synopsys, Inc.
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Quantum Safe Cryptography: Protecting Devices and Data in the Quantum Era
Bart Stevens
Senior Director of Product Marketing
Rambus, Inc.
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How will platform and communication security evolve in the quantum computing era?
Graeme Hickey
VP Engineering
PQShield
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The Power of Physical Unclonable Functions (PUFs)
Chris Jones
Director, Field Application
Crypto Quantique
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7.00 pm
You should not miss !
Wine tasting party sponsored by Soitec
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8.00 pm
Banquet sponsored by D&R |
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- Day 2 – December 5th, 2023
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9.00 am
Processor IP
Chairperson: Philippe Quinio – STMicroelectronics
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Beyond one-size-fits-all: The power of tailored CPUs
Mike Eftimakis
VP Strategy & Ecosystem
Codasip GmbH
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Survey of market available processor IP
Dagmara Zielinska
Partnership Program Manager
D&Rwith Gabrièle Saucier
CEO
D&R
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9.40 – 11.00 am
From Processor IP to Processor or supercomputer chip:
What is needed and what is the next success track ?
This panel gives an opportunity to exchange some vision about the future of processor IP up to extension to processor / multiprocessor chip.
With the participation of:
- Fabio Malatesta – Product Marketing Engineer – Frontgrade Gaisler
- Mike Eftimakis – VP Strategy and Ecosystem – Codasip GmbH
- Loic Lietar – Co-Founder & CEO – GreenWaves Technologies
- Thierry Lelégard – Head of Platform Security – SiPearl
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11.00 am
Break |
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11.30 am
Analog IP
Chairperson: Philippe Flatresse – SOITEC
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Adaptive Voltage Scaling (AVS): Enhancing Chip Efficiency
Vincent Telandro
Product Marketing manager (Power Management IP)
Dolphin Design
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Technology Analysis: what you need to know before embarking on analog design migration
Jean-François Lambert
Director of Business Development
Thalia
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12.15 pm
Lunch |
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1.20 pm
Design Platform
Chairperson: Philippe Flatresse – SOITEC
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Hybrid Cloud Management for IP Development
Sundar M
Director
Tessolve Semiconductor Private Limitedwith Pitchumani Guruswamy
Tessolve Semiconductor Private Limited
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Online Only
|
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A novel approach for SoC design resource management and prediction
Chouki Aktouf
Co-Founder
Innova Advanced Technologies
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Multi-IO co-processor with TSN
Vincent Laporte
CTO – V.P. BU
CetraC
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2.10 pm
Break |
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2.30 pm
Verification Platform
Chairperson: Patrick Blouet
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IP QA Best Practices
Lionel Couder
Sr. Applications Engineer
Siemens Digital Industries Software
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Important Considerations for Verification of CXL Devices
Nicolas Dai
Application Engineer Architect
Cadence Design Systems, Inc.
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3.10 pm
Monitoring Platform |
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Chip Condition Monitoring and Performance Optimization. Process/Voltage/Temperature Detectors in ASIC Design Methodology.
Vsevolod Sergeenko
RFID Team Leader
NTLab
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The Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases
Dan Alexandrescu
R&D Engineer
Synopsys, Inc.
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4.00 pm
Give Away – Event Closure |
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