The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A… Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
Verifying an SoC is an extremely complex process that requires agile turnaround, constant control feedback, and flexibility to adapt to evolving project needs. Coverage is an efficient metric for the number of potential bugs found… Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family
Synopsys Webinar | Wednesday, May 24, 2023 | 10:00 – 10:45 a.m. IST Engineering resources are getting stretched thinner and thinner as design complexity increases. Automation is a significant driver to help engineers overcome resource… Accelerate Coverage Closure and Debug with Synopsys AI-Driven Verification Solutions
Analyzing the thousands of failures from daily regression runs is a manual, tedious, and error-prone process. The process can significantly impact quality-of-results, time-to-results and cost-of-results. The Synopsys Verdi® Regression Debug Automation (RDA) is an artificial… AI-Driven Verification: Saving Time with Verdi Regression Debug Automation