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5X Faster Equivalence Checking with Formality ML-driven DPX

June 9, 2022 @ 10:00 am - 11:00 am PDT

Synopsys, June 9, 2022

Synopsys’ Fusion Compiler provides a broad spectrum of aggressive optimization techniques such as retiming, multibit banking and advanced data-path optimization that our designers want to take advantage of to achieve maximum PPA. Our expectation from production quality Equivalence checking is to be able to complete verification with minimal efforts and the fastest turn-around-time.

This presentation details how Formality with ML-driven Distributed Processing (DPX) delivered out of the box verification without the need to scale back optimizations or sacrifice PPA goals.


Listed below are the industry leaders scheduled to speak.

Avinash Palepu

Product Marketing Manager

Avinash Palepu is the Product Marketing Manager for Formality and Formality ECO products. Starting with Intel as a Design Engineer, he has held various design, AE management and Product Marketing roles in the semiconductor design and EDA industries. Avinash holds a Master’s degree in EE from Arizona State University and a Bachelor’s degree from Osmania University.

Woo Sung Choe

Principal Engineer
Samsung Electronics SLSI Division

Woo Sung Choe is a Principal Engineer at Samsung Electronics in the SLSI division. Over a span of 20 years, he has worked on advanced node ASIC and SoC design of AP, modem, and connectivity system engineering on various Samsung smartphone projects.

He has successfully contributed to the development of AP (Application Processor) for smartphones, tablets and wearable devices for the Exynos series 980, 9820, 2200 and modem chips for Galaxy mobile devices.

His specialization is in the low power design, high speed interface system and bus design based on ARM.


June 9, 2022
10:00 am - 11:00 am PDT
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