An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development

This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single “executable” specification.

Appropriate Audience:

● Architects/RTL Designers
● Verification Engineers
● Pre-Silicon Validation Teams
● Post-Silicon Lab Bring-up Team Members
● Technical Writers
● Firmware Engineers
● Embedded Programmers

Learn How To:

● Quickly and efficiently create correct-by-construction reusable designs
● Quickly and comprehensively verify registers and memories
● Swiftly generate device drivers
● Automatically generate derived documentation for Tech-Pubs, Lab, internal and external customers
● Eliminate inefficiencies in the design process
● Prevent errors from entering the system by giving appropriate error messages in the specification itself
● Carefully manage register information – and any inevitable changes – throughout the design process
● Increase entire development team productivity with auto generation of Register database information in the formats desired by the various teams.
● Reduce design cost by reducing iterations that result due to lack of accurate communication between various teams Specification Automation Benefits & Capabilities:
● Deliver the ease of a document editor to the system architect or designer for the creation of an executable specification
● Executable specification contains everything needed to fully describe the design including documentation and register descriptions
● All downstream views are generated from this single specification
● Dramatically increase productivity while reducing risk

Presenter Bio:

Nikita Gulliya, RnD Engineer, joined Agnisys in 2017 and serves on the product engineering team. A SystemRDL expert, she has led various SystemRDL trainings for Agnisys customers around the globe.

*This webinar is in partnership with SemiWiki and Agnisys