Design Robust IC Packages Faster Using In-Design SI/PI Analysis

IC package design teams and characterization teams have had a “throw-it-over-the-wall” relationship for decades, which often delays design releases by months. However, as signal integrity (SI) and power integrity (PI) challenges evolve with multi-die heterogeneous integration, the need to perform SI/PI analysis as part of the design flow has become a requirement to meet compressed design cycles.

Today, in-design analysis empowers IC package design teams to resolve problems and improve design quality long before the SI/PI teams become involved, ultimately shaving months from the average IC package design cycle.

This webinar will educate IC package designers and their managers about Cadence in-design analysis, which is now part of the market-leading Cadence IC package design technology. It will highlight a guided, easy-to-use integrated design and analysis workflow that addresses the complexity of electrical challenges, reduces design iterations, and saves millions of dollars in engineering time.

Speakers:

John Park

Product Management Group Director

John Park is Product Management Group Director for Advanced Semiconductor Packaging at EDA industry leader Cadence Design Systems, where he leads a team responsible for defining cross-domain solutions and methodologies for IC, package, and PCB co-design and analysis. His team is especially focused on developing tools and flows for chiplet-based 3D designs. He has over 40 years of experience in the EDA field and is regarded as an international expert on chiplets, packaging, and heterogenous integration.

Andy Haas

Sr. Principal Product Engineer

Andy Haas is a Product Engineer for In-Design Analysis and SI/PI Signoff at Cadence Design Systems. Andy has more than 20 years of experience in EDA product sales, support, architecture and management with particular focus on Signal Integrity, Power Integrity, and analog functional verification. He also has 10+ years of Mil-Aero systems, PCB and custom IC specification, design and analysis.