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FPGA Design Verification – Planning

September 7, 2023 @ 11:00 am - 12:00 pm PDT

Aldec, Verification

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes.


In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way.


In part 1 of this webinar series, we will provide an overview of advanced simulation-based verification process and outline the differences between ASIC and FPGA-centric verification processes. Then, we will show you how to develop a verification plan; describing WHAT to verify and HOW to verify it. Finally, we will talk about design verification of highly configurable design and IP blocks.



  • ASIC Verification vs FPGA Verification
  • FPGA-specific Design Verification Project Constraints
  • Overview of Design Verification Stages
  • Organizing FPGA Teams
  • Design Verification Methods
  • Stimulus and Checker Types
  • Block, Subsystem and System-Level
  • Verification Plan Structure
  • Setting Design Verification goals (WHAT)
  • Extracting Design Properties
  • Setting Priorities
  • Defining Verification Methods, Types and Levels (HOW)
  • Defining Test Scenario
  • Working with Configurable Designs
  • Demo with example design and testbench
  • Conclusion
  • Q&A


Webinar Duration:

  • 45 min presentation/live demo
  • 15 min Q&A


Presenter BIO

Alexander Gnusin, Design Verification Technologist, Aldec

Alexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.


September 7, 2023
11:00 am - 12:00 pm PDT
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