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International Symposium on Field-Programmable Gate Arrays
February 12, 2023 @ 8:00 am - February 14, 2023 @ 5:00 pm PST
The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2023, the 31st edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel.
Technical Program
All times shown in Pacific Standard Time (UTC-8).
All events in the San Carlos II-IV rooms and in the foyer, unless indicated otherwise.
Sunday, February 12, 2023
Workshops and Tutorials are listed separately. All workshops and tutorials are included in the conference fee, but may require separate registration in order to manage capacity. Check each event for additional registration requirements.
There is a 6:00pm Reception for all attendees in the San Carlos Ballroom Foyer.
Monday, February 13, 2023
★ indicates best paper candidate
| 9:00 am – 9:10 am | Opening |
| 9:10 am – 10:00 am | Keynote: Compiler Support for Structured Data Saman Amarasinghe, MIT |
| 10:00 am – 10:15 am | Break |
| 10:15 am – 11:30 am | Paper Session 1 – High-Level Abstraction and Tools Chair: George Constantinides, Imperial College London |
| DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLS★ Linus Y. Wong, Jialiang Zhang and Jing “Jane” Li |
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FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs    Linfeng Du, Tingyuan Liang , Sharad Sinha , Zhiyao Xie and Wei Zhang |
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Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking  Jiahui Xu, Emmet Murphy , Jordi Cortadella and Lana Josipović |
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| Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits (short paper) Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri , Lana Josipović and Paolo Ienne |
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| 11:30 am – 12:30 pm | Poster Session 1 |
| 12:30 pm – 2:00 pm | Lunch Ferrantes Bay View Ballroom |
| 2:00 pm – 3:15 pm | Paper Session 2 – Applications and Design Studies 1 Chair: Jeffrey Goeders, Brigham Young University |
| A Study of Early Aggregation in Database Query Processing on FPGAs Mehdi Moghaddamfar , Norman May , Christian Färber , Wolfgang Lehner and Akash Kumar |
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| FNNG: A High-Performance FPGA-based Accelerator for K-Nearest Neighbor Graph Construction Chaoqiang Liu, Haifeng Liu, Long Zheng, Yu Huang, Xiangyu Ye, Xiaofei Liao and Hai Jin |
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| ACTS: A Near-Memory FPGA Graph Processing Framework Wole Jaiyeoba and Kevin Skadron |
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| Exploring the Versal AI Engines for Accelerating Stencil-based Atmospheric Advection Simulation (short paper) Nick Brown |
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| 3:15 pm – 3:30 pm | Break |
| 3:30 pm – 5:00 pm | Paper Session 3 – Architecture, CAD, and Circuit Design Chair: Raymond Nijssen, Achronix |
| Regularity Matters: Designing Practical FPGA Switch-Blocks Stefan Nikolić and Paolo Ienne |
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| Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters★ Colin Drewes, Olivia Weng, Keegan Ryan , Bill Hunter, Christopher McCarty , Ryan Kastner and Dustin Richmond |
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| Post-Radiation Fault Analysis of a High Reliability FPGA Linux SoC Andrew Wilson, Nate Baker, Ethan Campbell, Jackson Sahleen and Mike Wirthlin |
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| FPGA Technology Mapping with Adaptive Gate Decomposition (short paper) Longfei Fan and Chang Wu |
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| Accurate Estimation of FPGA Routing Mux Usage and Routability Without Explicit Routing (short paper) Jonathan W. Greene |
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| 5:00 pm – 6:30 pm | Adjourn |
| 5:10 pm – 6:00 pm | Steering Committee Meeting Los Angeles Room |
| 6:30 pm – 8:30 pm | Banquet and Invited Panel on “Open-source and FPGAs: Hardware, Software, Both or None?” San Carlos Ballroom |
Tuesday, February 14, 2023
★ indicates best paper candidate
| 9:00 am – 9:10 am | Chair’s Announcement |
| 9:10 am – 10:00 am | Keynote: FPGAs and Their Evolving Role in Domain Specific Architectures: A Case Study of the AMD 400G Adaptive SmartNIC/DPU SoC Jaideep Dastidar, AMD |
| 10:00 am – 10:55 am | Paper Session 4 – Deep Learning Chair: Mohamed Abdelfattah, Cornell Tech |
| CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture Jinming Zhuang , Jason Lau , Hanchen Ye , Zhuoping Yang, Yubo Du , Jack Lo, Kristof Denolf, Stephen Neuendorffer , Alex Jones, Jingtong Hu , Deming Chen , Jason Cong and Peipei Zhou |
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| Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image Processing Alireza Khataei, Gaurav Singh and Kia Bazargan |
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| Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search (short paper) Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yaoyu Tao and Yuchao Yang |
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| 10:55 am – 11:10 pm | Break |
| 11:10 am – 12:30 pm | Paper Session 5 – FPGA-Based Computing Engines Chair: Peipei Zhou, University of Pittsburgh |
| hAP: A Spatial-von Neumann Heterogeneous Automata Processor with Optimized Resource and IO Overhead on FPGA Xuan Wang, Lei Gong, Jing Cao, Wenqi Lou , Weiya Wang , Chao Wang and Xuehai Zhou , Weiya Wang |
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| CSAIL2019 Crypto-Puzzle Solver Architecture★ Sergey Gribok, Martin Langhammer and Bogdan Pasca |
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| ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration Kan Shi , Shuoxiang Xu , Yuhan Diao , David Boland , Yungang Bao |
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| BOBBER A Prototyping Platform for Batteryless Intermittent Accelerators (short paper) Vishak Narayanan, Rohit Sahu, Jidong Sun and Henry Duwe |
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| 12:30 pm – 2:00 pm | Lunch Ferrantes Bay View Ballroom |
| 2:00 pm – 3:00 pm | Poster Session 2 |
| 3:00 pm – 4:10 pm | Paper Session 6 – Applications and Design Studies 2 Chair: Jing (Jane) Li, University of Pennsylvania |
| A Framework for Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform via On-Chip Dynamic Tree Management Yuan Meng , Rajgopal Kannan , Viktor K Prasanna |
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| Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi , Robert F. Lucas , Jason Cong |
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| Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA Sasindu Wijeratne, Ta-Yang Wang , Rajgopal Kannan , Viktor Prasanna |
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| 4:10 pm – 4:30 pm | Best Paper Award and Closing Remarks |
Poster Session 1 (February 13)
11:30am – 12:30pm
| Title | Authors |
|---|---|
| OMT: A Demand-Adaptive, Hardware-Targeted Bonsai Merkle Tree Framework for Embedded Heterogeneous Memory Platform | Raki Shadab, Yu Zou, Sanjay Gandham and Mingjie Lin |
| Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms | Kaveh Aasaraai , Emanuele Cesena, Rahul Maganti, Nicolas Stalder , Javier Varela and Kevin Bowers |
| AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture | Hyeong-Ju Kang |
| Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station | Tim Oberschulte, Jakob Marten and Holger Blume |
| Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization | Meghna Mandava and Deming Chen |
| Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks | Ruiqi Chen , Yuhanxiao Ma , Enhao Tang, Shun Li , Yanxiang Zhu , Haoyang Zhang, Jun Yu and Kun Wang |
| Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits | Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri , Lana Josipović and Paolo Ienne |
| HMLib: Efficient Data Transfer for HLS using Host Memory | Michael Lo , Young-kyu Choi , Weikang Qiao, Mau-Chung Chang and Jason Cong |
| An Efficient High-Speed FFT Implementation | Ross Martin |
| Weave: Abstraction for Accelerator Integration of Generated Modules | Tuo Dai, Bizhao Shi and Guojie Luo |
| A Novel FPGA Simulator Accelerating Reinforcement Learning-Based Design of Power Converters | Zhenyu Xu, Miaoxiang Yu, Qing Yang, Yeonho Jeong and Tao Wei |
| A Fractal Astronomical Correlator based on FPGA Cluster with Scalability | Lin Shu, Long Xiao, Yafang Song, Qiuxiang Fan , Guitian Fang and Jie Hao |
| Power Side-channel Countermeasures for ARX Ciphers using High-level Synthesis | Saya Inagaki, Mingyu Yang , Yang Li, Kazuo Sakiyama and Yuko Hara-Azumi |
| Single-Batch CNN Training using Block Minifloats on FPGAs | Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland and Philip Leong |
Poster Session 2 (February 14)
2:00pm – 3:00pm
| Title | Authors |
|---|---|
| FPGA Technology Mapping with Adaptive Gate Decomposition | Longfei Fan and Chang Wu |
| Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search | Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yuchao Yang and Yaoyu Tao |
| BOBBER A Prototyping Platform for Batteryless Intermittent Accelerators | Vishak Narayanan, Rohit Sahu, Jidong Sun and Henry Duwe |
| Accurate Estimation of FPGA Routing Mux Usage and Routability Without Explicit Routing | Jonathan Greene |
| Adapting Skip Connections for Resource-Efficient FPGA Inference | Olivia Weng, Gabriel Marcano , Vladimir Loncar , Alireza Khodamoradi , Nojan Sheybani, Farinaz Koushanfar , Kristof Denolf (Xilinx), Javier Duarte and Ryan Kastner |
| Multi-bit-width CNN Accelerator with Systolic-in-Systolic dataflow and Single DSP Multiple Multiplication Scheme | Mingqiang Huang, Yucen Liu, Sixiao Huang, Kai Li, Qiuping Wu and Hao Yu |
| Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation | Bharat Sukhwani, Mohit Kapur, Alda Sanomiya, Liran Schour, Martin Ohmacht, Chris Ward, Chuck Haymes and Sameh Asaad |
| LAWS: Large-Scale Accelerated Wave Simulations on FPGAs | Dimitrios Gourounas, Bagus Hanindhito , Arash Fathi, Dimitar Trenev , Lizy John and Andreas Gerstlauer |
| Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing | Shashwat Shrivastava, Stefan Nikolić , Chirag Ravishankar, Dinesh Gaitonde and Mirjana Stojilović |
| Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing Problems | Andrew Gunter and Steve Wilton |
| An FPGA-Based Weightless Neural Network for Edge Network Intrusion Detection | Zachary Susskind, Aman Arora , Alan Bacellar, Diego Dutra , Igor Miranda , Mauricio Breternitz Jr. , Priscila Lima , Felipe França , Lizy John |
| A Flexible Toolflow for Mapping CNN Models to High Performance FPGA-based Accelerators | Yongzheng Chen and Gang Wu |
| Exploring the Versal AI Engines for Accelerating Stencil-based Atmospheric Advection Simulation | Nick Brown |
| Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop Accelerators | Emanuele Del Sozzo , Davide Conficconi , Marco Santambrogio and Kentaro Sano |
| FPGA Acceleration for Sequential Interference Cancellation in Severe Multipath Acoustic Communication Channels | Jinfeng Li and Yahong Zheng |
| FreezeTime: Towards System Emulation through Architectural Virtualization | Sergiu Mosanu, Joshua Fixelle, Kevin Skadron and Mircea Stan |