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Introduction to Questa Lint and CDC for Designers

January 25 @ 10:00 am - 11:00 am PST

Questa, January 25, 2022

Have you ever had RTL code that passes simulation but still fails due to things like unreachable code, out-of-range violations, or incorrect order of execution? Have you ever dealt with a multi-clock design that had glitch or reconvergence issues in silicon that took weeks to root cause? See how the correct verification tools can resolve these types of problems before you signoff on your design.

Overview:

Simulation and Static Timing Analysis are great for first pass verification, but they are not sufficient for ASIC signoff level verification. Repeated rewriting and recompiling code (a.k.a. “burn and pray”) for FPGAs is an extremely slow and error prone way to insure your code is ready for release. To reach signoff/release level verification, other methodologies must be implemented that go beyond the tried and true techniques.

In this technical session, we focus on:

  • Why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block
  • What metastability is and how it will affect silicon bring-up
  • How addressing these points during the design process is critical to achieving tight schedules with limited resources

What You Will Learn:

  • How linting can improve RTL code
  • How to handle crossing clock domains in a multi-clock domain design

Who Should Attend:

  • ASIC, FPGA and IP Design and Verification Engineers & Managers and those interested in achieving higher quality RTL code and avoiding issues with multi-clock domain designs

Product(s) Covered:

  • Questa Lint
  • Questa CDC
Mathew Yee
Mathew Yee
Questa Design Solutions Applications Consultant
Siemens EDA

Mathew Yee is a lead Applications Consultant for Questa Design Solutions at Siemens EDA and has over 30 years of experience in engineering design, verification, and applications. Yee has held engineering and consulting services roles in electronics and EDA companies such as Amdahl, Applied Signal Technology, KC Technology, InnoLogic Systems, Synopsys, Axiom Design Automation, and SpringSoft. He holds a BSEE from UC Santa Barbara.

Details

Date:
January 25
Time:
10:00 am - 11:00 am PST
Event Category:
Event Tags:
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Website:
Event Website

Organizer

Siemens EDA
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