Optimal circuit sizing strategies for performance, low power, and high yield of analog and full custom IP

There have always been good reasons to port designs to new foundries or processes. These reasons have included reusing IP in new projects, moving an entire design to a smaller node to improve PPA, or second sourcing manufacturing. While there can be many potential business motivations for any of the above, in today’s environment with semiconductor supply shortages, design porting has taken on a new and compelling importance.

In many SOCs it is enough to find equivalent analog IP, for such things as PLLs and IO’s, but mixed signal designs that feature custom IP blocks need more attention. While it is never truly easy to port digital designs, as a result of the use of RTL, libraries, synthesis and P&R this task is tractable. Analog is quite another thing altogether.

Fortunately, MunEDA has a comprehensive solution for the analog design porting process, the WiCkeD-SPT Schematic Porting Tool. In this webinar we’ll show how quickly a new user can set up WiCkeD-SPT for correct and fast schematic conversions between different foundry PDKs. We’ll discuss automatic re-wiring, property mappings and symbol mappings that typically occur with schematic migration, as well as its integration into the analog IP migration flow.

Speaker: Michael Pronath (MunEDA) Michael is VP of Products & Solutions at MunEDA, and author and co-author of several international publications about methods of analog integrated circuit design and testing of mixed-signal circuits.