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How to Sign Off a 10 Billion+ Transistor Design in the Cloud

December 2, 2021 @ 9:00 am - 10:00 am PST

Cadence, December 2nd

Advanced semiconductor applications such as artificial intelligence / machine learning (AI/ML) and graphic processing units (GPUs) fully leverage dense, advanced-node technology to push the extreme limits of design size. To signoff such large designs, engineers are increasingly relying on distributed compute methods to accelerate the signoff analysis. Furthermore, given lack of scalability of on-premises compute resources, designers are migrating towards cloud-based solutions to solve their peak compute demand and meet their aggressive tapeout schedules.

In this CadenceTECHTALK, TSMC + Microsoft + Cadence will present a signoff methodology optimized for giga-scale class (10 billion+ transistor) designs and tailored for execution on cloud-based infrastructure. The talk will feature the Cadence® Tempus™ Timing Signoff Solution’s STA signoff tool and CloudBurst™ platform, as well as Microsoft Azure’s latest offerings suited for EDA workloads.

Featured Speakers

Vivian Jiang & Kurt Chiang,
Technical Managers,

Brandon Bautz, Sr. Group Director Product Management, Cadence

Prashant Varshney, Sr. Director Product Management, Microsoft

Ketan Joshi, Group Director, Cloud Business Development, Cadence


December 2, 2021
9:00 am - 10:00 am PST
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