| Time |
Topic |
Speaker |
| 09:15 – 09:45 |
Check-in and light breakfast |
|
| 09:45 – 10:00 |
Introduction of Real Intent and speakers |
Uri Farkash, Real Intent – Senior Sales Director |
| 10:00 – 10:30 |
Keynote Speaker |
Dr. Prakash Narain, Real Intent – President and CEO |
| 10:30 – 10:45 |
An Overview Static Sign-off |
Dr. Prakash Narain, Real Intent – President and CEO |
| 10:45 – 11:45 |
Connectivity Case Studies & Avoiding Glitch Bugs |
Oren Katzir, Real Intent – VP, Application Engineering |
| Polina Gemelfarb , Real Intent – Senior FAE |
| 11:45 – 12:15 |
Tutorial: Advanced RDC Verification |
Polina Gemelfarb , Real Intent – Senior FAE |
| 12:15 – 12:45 |
Expert Users Track: CDC Signoff – from Gamble to Certainty |
Milca Tarshish, Intel WCS – Senior VLSI Engineer |
| Doron Stein, Intel WCS – Senior CAD Engineer |
| 12:45 – 14:00 |
Lunch & Networking |
|
| 14:00 – 14:30 |
Expert Users Track: Best Practices for Static Sign-Off with Continuous Integration |
Itai Resh, Hailo – VLSI Project Lead |
| 14:30 – 15:15 |
Early DFT and Test gaps detection |
Oren Katzir, Real Intent – VP, Application Engineering |
| 15:15 – 15:45 |
Dynamic and Formal CDC |
Roman Paleria, Real Intent – FAE Manager |
| 15:45 – 16:15 |
Component Level CDC Workshop |
Evgeny Zhyvov, Real Intent – Principal Engineer |
| 16:15 – 16:30 |
Advancements in LINT |
Roman Paleria , Real Intent – FAE Manager |
| 16:30 – 16:45 |
Closing remarks & Prize draw |
Uri Farkash, Real Intent – Senior Sales Director |
