DVClub Europe – Cache Coherency Verification

• SoC cache coherency verification is one of the most complex challenges faced by verification engineers. And the introduction of the embedded L3 cache and the increasing number of cores in CPU clusters ais making it even more challenging. In this DVClub we will focus on how this challenge can be best approached and some automation added.

Agenda (BST)

12:00   Welcome and Introduction – Mike Bartley, Senior Vice President – VLSI Design, Tessolve
12:00    David Kelf, Breker Verification Systems
12:20    Sponsor Speaker
12:40    Sponsor Speaker
13:00    Close

Register now to become a part of this event. Free to attend online.

Mike Bartley, Senior Vice President – VLSI Design, Tessolve