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Silvaco UseRs Global Event – EMEA, 2025

January 21 @ 10:00 am - 5:00 pm GMT

Silvaco SURGE 2025

Silvaco will hold its annual SURGE users event on January 21, 2025.

SURGE brings the TCAD, EDA, and IP communities together to discuss new technologies, share users’ experiences, and discover innovative techniques for advanced semiconductor design.

AGENDA

Time General Session
10:00 Keynote – Babak Taheri, Chief Executive Officer and Director, Silvaco​
10:15 AI Takes EDA to the Next Level – Wally Rhines, President and CEO of Cornami and Silvaco Board Member​
10:30 NanoHub Workforce Development – Dr. Peter Griffin, Stanford University ​
Time SEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)
10:45M TCAD Update – Dr. Eric Guichard, SVP and GM of TCAD Business Unit, Silvaco​
11:00 Low-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi, Analog Engineer, Ciena
11:15 Machine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic, TU Vienna​
11:30 TBA – Sumeet Pandey, Micron Technologies​
11:45 Applying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat, TCAD Senior Staff FAE, Silvaco ​
12:05 Developing Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green, TCAD Applications Engineer, Silvaco​
12:25 Power Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor, Head of Modeling, Silvaco​
13:00 LUNCH BREAK​
Time IC Design Track (EDA and IP)​​
14:00 EDA and IP Updates – Dan Fitzpatrick, VP and GM of EDA Business Unit, Silvaco – Ben Louie, VP and GM of IP Business Unit, Silvaco​
14:20 EDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi, Staff Applications Engineer, Silvaco​
14:40 Jivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen, Director of Analog Design, Silicon Creations ​
15:00 Using Viso to Investigate, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz, Corporate Applications Engineer, Silvaco
15:15 Standard Cells Characterization Challenges and Improvement – Siti Mariyam, IP Design Enablement, SilTerra​
15:35 Low Voltage Standard Cell Operation at 3nm – Fernando Carrion, R&D Engineer, Silvaco​
16:00 Advanced Node Library Development with Cello FinFET – Felipe Bortolon, Engineering Manager IP, Silvaco​
16:20 LDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder, Director of Engineering, Silvaco – Shaikh A Shams, Staff Engineer, Silvaco​
16:35 Introduction to CAN-XL, Mauricio Brochi, Director of Automotive IP, Silvaco

Agenda subject to change.

Details

Date:
January 21
Time:
10:00 am - 5:00 pm GMT
Event Categories:
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Website:
Event Website

Organizer

Silvaco
View Organizer Website

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