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Silvaco UseRs Global Event – Japan, 2025

January 23 @ 10:00 am - 5:00 pm JST
Silvaco SURGE 2025
SURGE (Silvaco UseRs Global Event) is a worldwide event held by Silvaco.
SURGE is an event for discussing new technologies, sharing user experiences, and discovering innovative techniques for advanced semiconductor design in the fields of TCAD, EDA, and IP. The event will be held online. We look forward to your participation.
We will randomly select 8 lucky winners from those who participate on the day and fill out the questionnaire to receive a special prize.
(Domestic shipping only.)
Please take this opportunity to register for SURGE Japan.

Distribution : Online
distribution service : Zoom Meeting
Participation fee : Free
Language : English

After you register, you will receive a notification email.

AGENDA

Time General Session
10:00 AM Keynote – Babak Taheri, Chief Executive Officer and Director, Silvaco​
10:15 AM AI Takes EDA to the Next Level – Wally Rhines, President and CEO of Cornami and Silvaco Board Member​
10:30 AM NanoHub Workforce Development – Dr. Peter Griffin, Stanford University
Time SEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)
10:45 AM TCAD Update – Dr. Eric Guichard, SVP and GM of TCAD Business Unit, Silvaco​
11:00 AM​ Low-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi, Analog Engineer, Ciena
11:15 AM Machine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic, TU Vienna
11:30 AM​ TBA – Sumeet Pandey, Micron Technologies​
11:45 AM Applying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat, TCAD Senior Staff FAE, Silvaco
12:05 AM​ Developing Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green, TCAD Applications Engineer, Silvaco
12:25 AM​ Power Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor, Head of Modeling, Silvaco​
1:00 PM LUNCH BREAK
Time IC Design Track (EDA and IP)
2:00 PM EDA and IP Updates – Dan Fitzpatrick, VP and GM of EDA Business Unit, Silvaco – Ben Louie, VP and GM of IP Business Unit, Silvaco
2:20 PM EDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi, Staff Applications Engineer, Silvaco​
2:40 PM Jivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen, Director of Analog Design, Silicon Creations ​
3:00 PM Using Viso to Investigate, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz, Corporate Applications Engineer, Silvaco
3:15 PM Standard Cells Characterization Challenges and Improvement – Siti Mariyam, IP Design Enablement, SilTerra
3:35 PM Low Voltage Standard Cell Operation at 3nm – Fernando Carrion, R&D Engineer, Silvaco
4:00 PM Advanced Node Library Development with Cello FinFET – Felipe Bortolon, Engineering Manager IP, Silvaco​
4:20 PM LDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder, Director of Engineering, Silvaco – Shaikh A Shams, Staff Engineer, Silvaco
4:35 PM Introduction to CAN-XL, Mauricio Brochi, Director of Automotive IP, Silvaco

Agenda subject to change.

Details

Organizer

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