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Synopsys Technical Forum 2024

February 26 @ 12:30 pm - 4:45 pm PST

Synopsys, February 26, 2024

Please join us for our in-person Synopsys Technical Forum, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis, mask data prep, and lithography simulation solutions. The Tech Forum is peer-to-peer, giving you the opportunity to hear how your lithography colleagues have addressed the challenges of 3nm and beyond.

Join us for our in-person Synopsys Technical Forum, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing’s mask synthesis, mask data prep, and lithography simulation solutions.

Why Attend?

Synopsys provides industry-proven EDA solutions to meet the demands of today’s advanced IC manufacturing processes while setting the standard in platform flexibility to enable innovative and custom solutions for next-generation technology nodes. Synopsys’ comprehensive Mask Synthesis, Mask Data Preparation, TCAD, and Yield Management tools provide leading edge performance, accuracy, quality, and cost of ownership for all your production and development needs.

Who Should Attend?

The Synopsys Technical Forum provides OPC, RET, and MDP engineers and managers practical insight into upcoming industry trends and solutions for delivering the highest quality results from their lithography hardware.

Agenda at a Glance

Here’s an overview of what’s happening at the event!
Monday, February 26, 2024
  • 12:30 PM – 1:00 PM
    Registration & Lunch
  • 1:00 PM – 1:15 PM
    Welcome & Introduction
    Shankar Krishnamoorthy, GM, Corp Staff, Synopsys
  • 1:15 PM – 1:45 PM
    Distinguished Speaker: The Future of Semiconductor Manufacturing: ​ New Developments in Speed and Innovation
    Kazunari Ishimaru, Senior Managing Executive Officer, Silicon Technology Division, Rapidus Corp.
  • 1:45 PM – 2:15 PM
    Keynote: Data Preparation Evolution and Mask Quality Enhancement
    Jerry Chen, Deputy Director, TSMC EBO
  • 2:15 PM – 2:45 PM
    Progress on Curvilinear OPC at Intel
    Harsha Grunes, Senior Principal Engineer, Intel
  • 2:45 PM – 3:15 PM
    Advanced Correction Technologies to Optimize Memory Cell Performance
    MS Chiang, Principal Engineer, Winbond
  • 3:15 PM – 3:45 PM
    Advances in Computational Lithography Solutions for High NA EUV Manufacturing
    Michael Lam, Director R&D, Synopsys
  • 3:45 PM – 4:45 PM
    Thank You & Prize Drawing – Dessert Reception

Details

Date:
February 26
Time:
12:30 pm - 4:45 pm PST
Event Categories:
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Event Tags:
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Website:
Event Website

Organizer

Synopsys
View Organizer Website

Venue

San Jose Marriott
301 S Market Street
San Jose, CA United States + Google Map

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