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Tackling Advanced Analog FinFET Front-End Design Challenges with Better Methodologies
May 5 @ 11:00 am - 12:00 pm PDT
Analog engineers adopting advanced FinFET technologies face many challenges that were not present when using planar transistors.
Challenges in layout implementation have a direct impact on design specifications, and the luxury of over-margining is long gone. There are no third-order effects anymore, and managing layout effects, such as device and interconnect parasitics, variation, matching, and EM-IR, just to name a few, provide added challenges. The degrees of freedom once enjoyed with planar design are now greatly limited as FinFET devices are discrete by nature. Simulating an analog circuit without considering the layout effect is not very productive and will lead to a long design cycle. Is there a better way?
In this CadenceTECHTALK™, we will discuss some of the challenges and show how Cadence’s comprehensive and silicon-proven methodology addresses them. Learn how to facilitate conversation between design and layout engineers to simplify the time-consuming “back-and-forth.”
This event is ideal for analog circuit engineers and recommended for CAD engineers and layout designers.