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Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs
March 10 @ 11:00 am - 12:00 pm PST
Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification techniques such as constrained random verification with assertion-based verification (ABV) can be used to help identify ambiguous or incomplete requirements early in the design and verification process. The ability of assertions to increase the observability of the design can dramatically reduce debug time. Reducing the time spent debugging increases the time that can be spent searching for new bugs, leading to better verification quality.
- Introduction to requirements-based verification
- Verification completeness
- Coverage usage and types
- Assertions-based verification
- Assertions planning and definitions
- Developing functional coverage with SVA
- Checking design requirements with SVA
- Using SVA for RBV
- SVA for developing design requirements
- SVA for specifying RTL code properties
- SVA to increase design observability
- Achieving completeness in requirements verification
- Questions and Answers
- 45 min presentation/live demo
- 15 min Q&A
Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.