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Workshop on Open-Source EDA Technology
November 3, 2022 @ 8:00 am - 2:00 pm PDT
Virtually co-sponsored by ICCAD 2022 on November 3, 2022!
The WOSET workshop aims to galvanize the open-source EDA movement. The workshop will bring together EDA researchers who are committed to open-source principles to share their experiences and coordinate efforts towards developing a reliable, fully open-source EDA flow. The workshop will feature presentations and posters that overview existing or under-development open-source tools, designs and technology libraries. A live demo session for tools in advanced state will be planned. The workshop will feature a panel on the present status and future challenges in open-source EDA, and how to coordinate efforts and ensure quality and interoperability across open-source tools.
Registration
There is no registration fee. The workshop is virtual. Please register through Zoom to attend the live sessions.
Proceedings
The 2022 WOSET paper proceedings is available at WOSET 2022
Schedule
The 2022 WOSET schedule is available at WOSET Schedule. Please register through Zoom to attend the live sessions.
Organization
Co-Chairs
- Jose Renau, UC Santa Cruz (Co-Chair)
- Matthew Guthaus, UC Santa Cruz (Co-Chair)
Program Committee
- Matthew Guthaus, UC Santa Cruz
- Jose Renau, UC Santa Cruz
- Matthew Venn, YosysHQ & ChipFlow
- Rajit Manohar, Yale University
- Scott Temple, University of Utah
- Jonathan Balkind, UC Santa Barbara
- Tobias Grosser, University of Edinburgh
Web Chairs
- Jesse Cirimeli-Low, UC Santa Cruz
- Sakshi Garg, UC Santa Cruz
Papers 1
| Time (PST) | Duration (Minutes) | Article # | Author(s) | Title |
|---|---|---|---|---|
| 8:00 AM | 20 | 12 | Wijerathne, Li, Karunarathne, Mitra, Peh | Morpher: An Open-Source Integrated Compilation and Simulation Framework for CGRA |
| 8:20 AM | 20 | 20 | Xu, Xiao, Luo, Liang | A MLIR-Based Hardware Synthesis Framework |
| 8:40 AM | 20 | 10 | Zhu, Yin, Wang, Tan | GreenRio: A Modern RISC-V Microprocessor Completely Designed with An Agile Open-source EDA Flow |
| 9:00 AM | 20 | 5 | Goldstein, Edwards | Accessibility of Chip Design to the Non-Professional |
| 9:20 AM | 20 | 9 | Manohar | xcell: a cell library characterizer for combinational and state-holding gates |
| 9:40 AM | 20 | 18 | Liang, Edwards | IRSIM: A Switch-Level Simulator and Dynamic Power Analysis Tool |
Poster Presentations
| Time (PST) | Duration (Minutes) | Article # | Author(s) | Title |
|---|---|---|---|---|
| 10:00 AM | 60 | 4 | Kashif, Ahmed, Karim | Bitstream Chef |
| 6 | Shahzaib, Kashif, Ahmed, Karim | SoC-Now: An Open-Source Web based RISC-V SoC Generator | ||
| 7 | Jia, Luo, Lu, Liang | TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra | ||
| 8 | Ahmed, Cirimelli-Low, Guthaus | OpenRegFile: Open-Source Register File Generation | ||
| 13 | Schoeberl, Pezzarossa | From Chisel to Chips with Open-Source Tools | ||
| 16 | Jayaraman, Huang, Renau | The Hardware Interchange Format | ||
| 17 | Kemmerer | PipelineC: Easy open-source hardware description between RTL and HLS |
Papers 2
| Time (PST) | Duration (Minutes) | Article # | Author(s) | Title |
|---|---|---|---|---|
| 11:00 AM | 20 | 1 | Birch | Open source FPGA-based emulation with Nexus |
| 11:20 AM | 20 | 11 | Eriksson, Vora | A Java Backend for ESSENT |
| 11:40 AM | 20 | 19 | Korbel | Rapid Open Hardware Development Framework |
| 12:00 PM | 20 | 3 | Agostini, Curzel, Limaye, Amatya, Minutoli, Castellana, Manzano, Ferrandi, Tumeo | SODA Synthesizer: an Open-Source, End-to-End Hardware Compiler |
| 12:20 PM | 20 | 2 | Euphrosine | Accelerate Silicon Design with Jupyter Notebooks |
| 12:40 PM | 20 | 15 | Hugg | 8bitworkshop: An Interactive Verilog Learning Tool |
| 1:00 PM | 20 | 14 | Nishizawa, Nakura | Library characterizer for open-source VLSI design |