Events

Boost LPDDR5 Verification from IP to System Level

Overview Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth, better performance and extended latencies for multiple use cases. Ensuring that JEDEC low-power double data rate 5 (LPDDR5) specification and overall… Read More »Boost LPDDR5 Verification from IP to System Level

Methodics User Group – November

Join our monthly session with Methodics IPLM experts and other users for open discussion, Q&A, and product demos. Next Session: November 9 | 1:00 P.M. EST Each 45-minute session offers a new opportunity to: Learn/share best practices. Interact with and learn from other users. Have Q&A time with our product experts on usage and methodology.… Read More »Methodics User Group – November

Jasper User Group 2021

It’s time for our annual formal verification user group CadenceCONNECT: Jasper User Group 2021. This in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence® JasperGold® formal verification technologies and methodologies. This user group  has become the premier industry event for formal experts… Read More »Jasper User Group 2021

Virtual Prototyping Day – Silver: Accelerate Your Innovation with Virtual ECUs

Synopsys invites you to the Virtual Prototyping Day – Silver, a virtual event on virtual ECUs and applications in automotive software development. Users share their experiences with the latest techniques and methodologies using Synopsys Silver virtual ECUs. Attendees will learn about how Silver supports new trends and industry standards in automotive with presentations by Daimler,… Read More »Virtual Prototyping Day – Silver: Accelerate Your Innovation with Virtual ECUs

Enabling Effective Design & Layout Collaboration for Next Generation Analog and Mixed-Signal Designs

Analog designers appreciate the importance of tight communication between layout and design teams, yet with geographically dispersed teams this can be a big challenge. Close collaboration between circuit designer and layout designer is essential for creating high-quality analog layouts. With this close connection and sharing feedback in a consistent way, analog designers can be sure… Read More »Enabling Effective Design & Layout Collaboration for Next Generation Analog and Mixed-Signal Designs

The Evolution of Process TCAD in Semiconductor R&D and Manufacturing

Shela Aboud, Ph.D., Synopsys Today, nearly every aspect of an integrated circuit is designed using EDA software. Technology computer aided design (TCAD) tools are used for modeling front-end-of-line manufacturing, including the fabrication and electrical characterization of individual transistors. I will discuss how TCAD has evolved to keep up with technology evolution and how new drivers… Read More »The Evolution of Process TCAD in Semiconductor R&D and Manufacturing

What’s Needed to Perform End-to-End Testing for 5G Open Radio Access Network SoCs

Testing an O-RAN Radio Unit (O-RU) SoC at full scale implies sending realistic traffic, in conformance with current specifications and at the right time on the right interfaces to simulate complex scenarios and cover as many corner cases as possible. It requires a robust debug methodology which can provide quick turn around and appropriate window… Read More »What’s Needed to Perform End-to-End Testing for 5G Open Radio Access Network SoCs

Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that cause massive, team-wide disruptions. This webinar takes you through example tool flows that, when used within a Continuous Integration (CI) system, can avoid or even eliminate those bugs and disruptions.… Read More »Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

Accelerating Analog Layout

The growing demand for analog features on IoT devices means that analog designers are under constant pressure to complete more designs faster than ever. For most layout designers, analog layout remains a largely manual task, which creates real challenges for today’s pressured designers. Pulsic presents a new solution for analog layout automation. Animate Preview accelerates… Read More »Accelerating Analog Layout

A Scalable Approach to 2X Faster Turnaround Time for Arm Neoverse N2 Core Design Verification

In the latest generation of multiple processor SoCs, designers are adding cache-coherent agents beyond the multi-processor clusters, making it a complex verification challenge. System coherency needs to be maintained at various levels, beginning at the cluster level, and continuing, across the cache coherent interconnect and across chips through chip-to-chip gateways. The coherency protocol across interconnects… Read More »A Scalable Approach to 2X Faster Turnaround Time for Arm Neoverse N2 Core Design Verification

Accelerate Semiconductor Technology Development and Innovation

Seminar Overview Join our online TCAD Seminar to learn about the application of Synopsys TCAD solutions to accelerate the research, development and optimization of semiconductor technologies. The seminar tracks cover all major semiconductor technologies, from advanced logic and memory to analog, power and optoelectronics. The solutions presented in this seminar are based on the industry-standard… Read More »Accelerate Semiconductor Technology Development and Innovation