IP
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IP Lifecycle Management for Chiplet-Based SoCs
Chiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups, DoD projects, and academic research. Chiplet-based architectures bring their own set of challenges however, especially in the context of IP… IP Lifecycle Management for Chiplet-Based SoCs
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Hot Chips 2023
Stanford University 471 Lagunita Drive, Stanford, CA, United StatesHot Chips 2023 (advance program) will be held as a hybrid conference with in-person attendance at Stanford University from August 27 to 29, 2023. Conference Format Hot Chips 2023 will be a hybrid conference. You may register to attend virtual or in-person. The conference venue is the Dinkelspiel Auditorium on the Stanford University Conference. Sunday… Hot Chips 2023
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UCIe-Based Chiplet Verification – from IP to SoC
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence,… UCIe-Based Chiplet Verification – from IP to SoC
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Accelerating Mainstream Adoption of Multi-Die Systems
Synopsys recently hosted a panel discussion with Ansys, Bosch, Intel, and Samsung to share their insights on the rapid adoption of multi-die systems. We invite you to the public broadcast of the panel where each company shares their view on the groundbreaking technology, what challenges lie ahead, and how companies can realize the promise of… Accelerating Mainstream Adoption of Multi-Die Systems
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Advanced Testbench for a Complex DUT
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more… Advanced Testbench for a Complex DUT
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IEEE SOCC 2023
Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA, United StatesSoCs and SiPs for Edge Intelligence and Accelerated Computing System-on-Chip (SoC) and System-in-Package (SiP) devices, comprising digital, analog, optical, RF, and Micro-Electro-Mechanical Systems (MEMS) are foundations of ubiquitous embedded high-performance computing (HPC). Such systems will provide solutions in communication, entertainment, medical and smart mobility technologies underpinning emerging “Digital Societies”. Recent advances in systems, packaging and process technologies are… IEEE SOCC 2023
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DVCon Taiwan 2023
National Yang Ming Chiao Tung University 300, Hsinchu City, TaiwanThe Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. Conference Sponsor: Accellera Global Sponsors: Synospys, Cadence, Siemens
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FPGAworld Conference 2023 – Stockholm
ÅF Frösundaleden 2A, 169 70 Solna, SwedenThe FPGAworld Conference is an international forum for researchers, engineers, teachers, students, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC-based products, educational & industrial cases, and more. Registration for attendees is free and includes 2*coffee, lunch and go-home drink. Keynote Speaker Copenhagen and Stockholm 2023 Keynote speaker: Martin Kellermann , Microchip… FPGAworld Conference 2023 – Stockholm
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CadenceLIVE Boston 2023
Boston Marriott Burlington One Burlington Mall Road, Burlington, MA, United StatesCadenceLIVE Boston 2023 – experience the power of intelligent system design - brings together users, developers, and industry experts to network, share ideas, and inspire design innovation in the most complex electronics and intelligent systems. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. Attendees will be able to… CadenceLIVE Boston 2023
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AI Hardware & Edge AI Summit
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesThe combined AI Hardware & Edge AI Summit comprehensively covers the design and deployment of ML hardware and software infrastructure across the cloud-edge continuum. For Enterprise ML Experts: Attend a unique AI systems event that will give you both hardware and software tools and techniques for training, deploying, and serving machine learning – the program contains… AI Hardware & Edge AI Summit
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NoC IP- Transforming Chip Communication
Webinar Agenda : Introduction to Mesh and Crossbar Architecture Cache Introduction Support for latest AMBA 5 Safety and security features as ASIL Standard. Port configurabilities Who Should Attend: Professionals working on development of NoC IP. People keen to know how NoC IP is shaping new era of chiplet communications Freshers in the field of VLSI… NoC IP- Transforming Chip Communication
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DVCon India 2023
Radisson Blu Outer King Road, Bengaluru, IndiaOn behalf of the DVCon India 2023 steering committee, it is my pleasure to welcome you all to the 8th edition of the Design and Verification Conference in India planned from 13- 14th September 2023 as an In-Person conference. We want to carry forward the momentum, excitement and the enthusiasm witnessed during last year’s edition into… DVCon India 2023