IP
FPGA Frontrunner Meet & Greet
Leonardo EH5 2XS, Edinburgh, United KingdomTechNES is pleased to announce the next FPGA Front Runners event – to he hosted by Leonardo at their venue in Edinburgh on March 29th, and will focus on FPGA… Read More »FPGA Frontrunner Meet & Greet
SNUG Silicon Valley 2023
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesSince 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today, as the electronics industry’s largest user conference, SNUG brings… Read More »SNUG Silicon Valley 2023
Versal Adaptive SoCs ONLINE WORKSHOP
Standard Level - 2 sessions (4 hours per session including breaks) With thanks to AMD Xilinx for sponsoring this workshop: It is available to attend FREE OF CHARGE (Usual price $990) March… Read More »Versal Adaptive SoCs ONLINE WORKSHOP
How to Achieve Seamless Deployment of Level 3 Virtual ECUs for Automotive Digital Twins
Driven by the trend towards software-defined vehicles (SDV), more complex software stacks are now being integrated into innovative automotive E/E architectures. Today the early integration testing of automotive software is already supported… Read More »How to Achieve Seamless Deployment of Level 3 Virtual ECUs for Automotive Digital Twins
Latch-Up 2023
University of California, Santa Barbara Santa Barbara, CA, United StatesThe FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of Friday, March 31 to Sunday, April 2, 2023… Read More »Latch-Up 2023
ISQED 2023
Seven Hills Conference Center 800 Font Blvd, San Francisco, CA, United StatesThe 24th International Symposium on Quality Electronic Design (ISQED'23) is the premier interdisciplinary and multidisciplinary Electronic Design conference—bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging,… Read More »ISQED 2023
Choosing the best modeling abstraction for your analysis
This webinar cover the modeling abstraction in the design of electronics, semiconductors and software. This webinar will definitely improve your modeling skills! --Is the abstraction right for your application and… Read More »Choosing the best modeling abstraction for your analysis
Enhance Productivity with Machine Learning in the Analog Front-End Design Flow
Advanced semiconductor nanometer technology nodes, together with smart IC design applications enable today very complex and powerful systems for communication, automotive, data transmission, AI, IoT, medical, industry, energy harvesting, and… Read More »Enhance Productivity with Machine Learning in the Analog Front-End Design Flow
User2User North America
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesU2U is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools. U2U is focused on these areas: Analog/Mixed-Signal Verification Calibre… Read More »User2User North America
Analog Layout with Thomas Parry and Tim Edwards
In this webinar we will take the comparator circuit from last time and look at how to do the layout with the 2 most used open source layout tools. We… Read More »Analog Layout with Thomas Parry and Tim Edwards
CadenceLIVE Silicon Valley 2023
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesJoin us for CadenceLIVE™ Silicon Valley 2023, held on April 19-20 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design… Read More »CadenceLIVE Silicon Valley 2023
Taking the Risk out of RISC-V with Fast, Architecture-Driven, PPA Optimization
The use of the RISC-V ISA to develop processors for SoCs is a growing trend. An important driver is the ability to customize or create ISA and micro-architectural extensions to… Read More »Taking the Risk out of RISC-V with Fast, Architecture-Driven, PPA Optimization