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Taking the Risk out of RISC-V with Fast, Architecture-Driven, PPA Optimization
April 20 @ 10:00 am - 11:00 am PDT
The use of the RISC-V ISA to develop processors for SoCs is a growing trend. An important driver is the ability to customize or create ISA and micro-architectural extensions to differentiate designs across application areas including AI, machine learning, automotive, data center, mobile, and consumer. Traditionally, designing proprietary cores with the right extensions has been challenging given the high degree of complexity and the high level of expertise required. Evaluating the impact of design decisions on power, performance and area (PPA) can pose a significant hurdle. This webinar will cover two products from Synopsys’ portfolio of industry leading tools: Synopsys ASIP Designer and Synopsys RTL Architect. These tools help designers create highly customized processors faster while meeting the desired PPA targets with confidence. The solutions facilitate the Synthesis-in-the-Loop design approach, both during earlier architectural design stages with processor model modifications and during RTL implementation. A real-world case study will highlight their interoperability and the results that can be achieved.
Jim is a Senior Product Manager at Synopsys. As a designer, his experience includes physical verification, design planning and design implementation on CPUs, networking, and security chips. As a product engineer, he supported design implementation, design planning, and package design at various EDA companies.
Maria joined the ASIP Designer R&D Team in 2019 where she focuses on the ASIP Designer’s HDL Generator tool, including synthesis support for ASIPs. Before joining Synopsys, she worked as a researcher at the Institute for Communication Technologies and Embedded Systems (ICE) at RWTH Aachen University.
*This webinar is in partnership with SemiWiki and Synopsys*