IP
Events
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Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
Abstract One commonality across semiconductor market segments is the need for memory. However, memory characteristics and interfaces vary greatly depending on the market segment and application. This webinar will focus on a specific class of memory devices – targeted to mobile and IoT applications – that use “SPI” (Serial Peripheral Interface) signaling. SPI was developed by Motorola… Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
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AI Hardware Summit
AI Hardware is evolving – and so are we! As machine learning models continue to grow in size and complexity, and more and more models enter production in enterprises worldwide, the way we approach accelerating these workloads is changing. At the front end, data-centricity is taking precedence over model-centricity. At the back end, AI practitioners… AI Hardware Summit
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How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
In this webinar, Synopsys and Arm describe how their recent collaboration helps maximize system performance and shorten Arm-based SoC design cycles. Learn how to minimize HPC/data center SoC design risk and ensure end-to-end IP integration, using available Arm reference designs and interoperability reports. Find out how Synopsys’ interface IP for the most widely used protocols… How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
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GF Technology Summit 2021
DELIVERING A NEW ERA OF MORE Semiconductor chips are pervasive—inside everything from appliances to thermostats, smartphones to automobiles, and industrial equipment to medical devices. These incredibly complex feats of human ingenuity power our world, fuel the global economy and enrich our lives. The GF Technology Summit offers an opportunity to discuss the challenges and opportunities in semiconductor design and… GF Technology Summit 2021
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Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
When verifying large SoC designs, one needs to write SystemVerilog models for analog/mixed-signal blocks to comply with the digital verification flow, such as UVM. This talk addresses ways to extract those models automatically from circuits. The first approach is called structural modeling, mapping each device in the circuit to an equivalent model in SystemVerilog and… Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
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ARC Processor Virtual Summit 2021
Why Attend? Join us for the ARC® Processor Virtual Summit to hear our experts, users and ecosystem partners discuss the most recent trends and solutions that impact the development of SoCs for embedded applications. This multi-day event will provide you with in-depth information from industry leaders on the latest ARC processor IP and related hardware/software… ARC Processor Virtual Summit 2021