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How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
September 15 @ 10:00 am - 11:00 am PDT
In this webinar, Synopsys and Arm describe how their recent collaboration helps maximize system performance and shorten Arm-based SoC design cycles. Learn how to minimize HPC/data center SoC design risk and ensure end-to-end IP integration, using available Arm reference designs and interoperability reports. Find out how Synopsys’ interface IP for the most widely used protocols such as PCIe, CXL, DDR5 and Die-to-Die has been enhanced with specific capabilities for the Arm Neoverse platform.
Attendees will learn about
- The companies’ collaboration to eliminate design bottlenecks so SoC designers can focus on their core competencies
- How the Synopsys and Arm IP collaboration maximizes system performance for HPC and data center SoCs
- Technical enhancements to Synopsys Interface IP to improve Arm-based SoC performance
- The details of Arm-validated interoperability testing of Synopsys DesignWare Interface IP portfolio
- Need for pre-Silicon Server Base System Architecture (SBSA) testing to meet SystemReady certification