Webinar
-
-
Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification
High-level design techniques and automation tools to address the limitations of traditional RTL, reduce verification times, improve performance, and manage growing design complexity—integrating seamlessly. What You'll Learn: This Lunch & Learn offers an in-depth look at Rise Design Automation tools and illustrates how high-level design and early verification techniques can bring value to your projects.… Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification
-
ASIP University Day 2024: Domain-Specific Processor Design using ASIP Designer
The AI revolution and other application domains, like data centers, advanced wireless communications, image and video processing, automated driving assistance, and post-quantum cryptography need more powerful architectures with higher performance. This is driving demand for heterogeneous multicore systems including application specific instruction set processors (ASIPs). ASIPs have become a mainstream implementation option for modern SoCs,… ASIP University Day 2024: Domain-Specific Processor Design using ASIP Designer
-
Tessolve AI Strategy & Eco System for DV
With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification, Tessolve has been working on improving internal DV processes, with impressive reductions in both effort and costs, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short… Tessolve AI Strategy & Eco System for DV
-
AI-Driven Constraint Generation for PCB and IC Package Design
Join our webinar to discover how AI-driven optimization and automation in constraint generation can boost productivity and shorten design cycles for PCB and IC package design. Learn how integrating Allegro X and Sigrity X can streamline your workflow. Key Takeaways: Learn how the Sigrity Topology Workbench, a robust system-level SI/PI environment for what-if and pre-route… AI-Driven Constraint Generation for PCB and IC Package Design
-
Optimize Systems and Semiconductor Architecture for Deep Learning Algorithms Using System-Level Modeling
In a world where artificial intelligence and machine learning are embedded in critical applications—from real-time tracking and object detection to autonomous systems—the architecture behind these innovations must be both powerful and efficient. To help engineers and architects address these challenges, our upcoming webinar will demonstrate how System-Level Modeling can be a game-changer in optimizing the performance and… Optimize Systems and Semiconductor Architecture for Deep Learning Algorithms Using System-Level Modeling
-
Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design
The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC, GPU, mobile, and AI/ML. Multi-die design technology has been quickly evolving with early experiences leading to the development of more advanced implementation and analysis techniques. For the past years, Synopsys and Ansys have… Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design
-
Fast Track RTL Debug with the Verisium Debug Python App Store
Working with debugging scripts locally and manually can be challenging, as can reusing and organizing them. What if there was a way to create your own app with the required functionality and to register it with the tool? The answer lies in the Verisium Debug Python App Store. Instantly add additional features and capabilities to… Fast Track RTL Debug with the Verisium Debug Python App Store
-
Webinar 2: Tessolve AI assisted DV Flow
With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification, Tessolve has been working on improving internal DV processes, with impressive reductions in both effort and costs, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short… Webinar 2: Tessolve AI assisted DV Flow
-
Boost your verification productivity with Questa Verification IQ
This session will explore Questa Verification IQ (VIQ), Siemens EDA’s next-generation collaborative and data-driven verification solution. VIQ revolutionizes the verification process by providing advanced analytics, enhanced collaboration, and comprehensive traceability. By leveraging machine learning, VIQ significantly enhances verification efficiency to boost your productivity. What you will learn: How to implement a collaborative, plan-driven verification process,… Boost your verification productivity with Questa Verification IQ
-
Accelerating Electric Vehicle Development: Integrated design flow for power modules with functional safety and reliability focus
This webinar to delve into the integrated design flow for power modules for electric vehicles (EVs) for enhanced functional safety and reliability. The power modules are distinguished by their high voltage and current requirements, substantial power dissipation, and the resulting temperature rise. Ensuring their safety and reliability is paramount. We will explore how Cadence’s cutting-edge… Accelerating Electric Vehicle Development: Integrated design flow for power modules with functional safety and reliability focus
-
FPGA Front Runner: FPGA Safety and Security
The Cass Centre Shaftesbury Road, Cambridge, United KingdomThis event covers the challenges in ensuring an FPGA is secure and demonstrably safe as per the relevant industry safety standards. This includes supply chains, FPGA hardware and the IP used on the FPGA Agenda (GMT) Time Speaker Details 09.30 Arrival and registration 10.00 Tobias Adryan, Synopsys Securing FPGAs Beyond the Bitstream 10.30 Espen Tallaksen,… FPGA Front Runner: FPGA Safety and Security
-
Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases
Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification, Tessolve has been working on improving internal DV processes, with impressive reductions in both effort and costs, and with many clients to improve both efficiency and quality… Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases