Webinar
SPICE-accurate variation-aware verification best practices with Solido AI-powered technologies
The demand for Custom ICs is on the rise globally along with high proliferation of semiconductor content. Higher requirements on power, performance, area, and yield, as well as other factors such as advanced process nodes and mission-critical applications have increased the need for accurate verification across process, voltage, and temperature corners, as well as local… Read More »SPICE-accurate variation-aware verification best practices with Solido AI-powered technologies
Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity
Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1, 2.0 and 3.0, Siemens Avery CXL Verification IP. Compute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as… Read More »Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity
From code to solution: tools and tactics for aerospace fault code troubleshooting
Join us in this insightful webinar as we delve into the world of aerospace and defense electrical fault code troubleshooting, unveiling the power of Capital™ Service Explorer. Discover innovative strategies to diagnose issues swiftly, minimizing downtime and optimizing product performance. Explore real-world examples showcasing how Capital Service Explorer facilitates the identification of commonalities among multiple… Read More »From code to solution: tools and tactics for aerospace fault code troubleshooting
Manufacturing driven design – DFM within an Xpedition Flow
We often think of Design for Manufacturing (DFM) as the sole responsibility of the fabricator. Over the years, many OEMs have implemented DFM as a final check in their release process, but that approach does not prevent issues within a design from piling up and being left for a DFM engineer to identify and communicate… Read More »Manufacturing driven design – DFM within an Xpedition Flow
Navigating the Power Challenges of Datacenter Infrastructure
The surge in applications such as AI, HPC, and GPU-intensive workloads requires unparalleled performance, placing cloud vendors and enterprise datacenters under immense pressure to simultaneously maximize power efficiency, reduce costs, and adhere to stringent environmental standards. Join us for a 1-hour panel discussion featuring unique perspectives from industry experts at Intel, Microsoft, Arm and proteanTecs. We will explore… Read More »Navigating the Power Challenges of Datacenter Infrastructure
Efficient Design Methodology for 112G Interface Compliance
As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet 112G compliance, companies can take extra steps to… Read More »Efficient Design Methodology for 112G Interface Compliance
What’s New About Virtuoso Layout Suite?
Accelerate Layout Creation with Automated Place and Route in Virtuoso Studio How can you cut down custom layout implementation from days to minutes? Custom device-level automated place and route (APR) for advanced nodes has very different requirements than mature node chip assembly routing. With our new unified APR flow-based user interface integrating the various automation… Read More »What’s New About Virtuoso Layout Suite?
New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset circuitry, and the intermixing of IPs with different reset schemas, power-management domains, and security domains or functionality. This increase in reset signaling complexity is creating new RDC verification challenges that… Read More »New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Virtuoso – Save on Signoff Effort with In-Design DRC and Fill
Virtuoso Layout Suite has pioneered in-design DRC checking and fixing in the layout editor. However, many of you have realized that the lack of completeness of rules in the techfile has caused many violations to fall through the cracks and are discovered later during signoff. An in-design DRC checking with signoff rule decks often comes… Read More »Virtuoso – Save on Signoff Effort with In-Design DRC and Fill
DVClub Europe: Latest VHDL Verification Techniques
This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM Agenda (GMT) 13:00 Welcome and Introduction – Mike Bartley, Tessolve 13:00 Epsen Tallaksen, EmLogic - Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) 13:30 Jim Lewis, SynthWorks - OSVVM in a NutShell, VHDL’s #1 Verification Methodology 14:00 Close Additional… Read More »DVClub Europe: Latest VHDL Verification Techniques
Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
With the growing complexities of 3D-ICs, chiplets, advanced packaging, and high-performance boards, engineers need a unified solution that provides early insight and analysis to detect and correct design problems before it is too late. This solution must also offer the ability to simulate the entire design efficiently, providing confidence in system signoff. Join our webinar… Read More »Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
High-Performance RTL Simulation Workflow with Vivado and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… Read More »High-Performance RTL Simulation Workflow with Vivado and Active-HDL