CadenceLIVE India
Radisson Blu Outer King Road, Bengaluru, IndiaCadenceLIVE India 2023 will be held on August 9-10 at the Radisson Blu Bengaluru Outer Ring Road. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users, developers, and industry experts to connect, share ideas, and inspire design creativity. Attendees have the opportunity to attend… Read More »CadenceLIVE India
Step-by-Step Guide for Your UCIe Design Verification
As traditional Moore’s law scaling approaches its physical limits, the industry is moving towards multi-die solutions for higher electronics system densities. Multi-die designs present one way for engineers to pack more functionality into silicon chips and improve yield without affecting fabrication feasibility or project budgets. The Universal Chiplet Interconnect Express (UCIe) standard was introduced in… Read More »Step-by-Step Guide for Your UCIe Design Verification
Dealing with Inconclusive Formal Proofs
Webinar Overview: Formal proofs of end-to-end properties can be a very valuable contribution to RTL sign-off and yet are often the most difficult to achieve. In this webinar Doulos Senior Member Technical Staff, Doug Smith will explore some practical ways of dealing with inconclusive formal proofs when using Jasper by Cadence . This includes the… Read More »Dealing with Inconclusive Formal Proofs
UCIe: On-Package Chiplet Innovation Opportunities
High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure to meet the demands of today’s data centers, autonomous vehicles, etc. On-package interconnects are a critical component to deliver the power-efficient performance for this evolving landscape. Universal Chiplet Interconnect Express (UCIe), is an open industry standard with a fully specified stack… Read More »UCIe: On-Package Chiplet Innovation Opportunities
Using Generative AI for ASIC Design
Tools like ChatGPT can be used for a variety of purposes, including writing Verilog. Unfortunately, these models are not (yet) perfect, and the quality of the output varies heavily depending on how you use them. Just as models may "hallucinate" facts they are not certain about, they can also "hallucinate" buggy and non-functional Verilog. In… Read More »Using Generative AI for ASIC Design
Advanced Analog Design Using S-parameters
This webinar highlights the importance of S-parameters to IC design and how Semtech Corporation, a high-performance semiconductor, IoT systems and Cloud connectivity service provider, utilizes Siemens AFS XT simulation technology to accelerate Semtech’s design process without compromising on accuracy to develop differentiated analog solutions for wired and wireless applications. Two case studies of analog circuits… Read More »Advanced Analog Design Using S-parameters
ERI 2.0 Summit
Hyatt Regency Seattle 805 Howell Street, Seattle, WA, United StatesWatch as leaders from our government agencies, the Defense Industrial Base, and prestigious universities bring unique and indispensable perspectives on our domestic semiconductor industry, national and economic security, and future research directions. The Electronics Resurgence Initiative (ERI), DARPA’s response to national-level microelectronics concerns, is designed to ensure U.S. leadership in cross-functional, next-generation microelectronics research, development,… Read More »ERI 2.0 Summit
MIPI A-PHY & MASS – Revolutionizing Automotive Connectivity
1) Intro - MASS introduction 2) Usage - Full chip automotive systems from peripheral to processor and vice versa. E.g.Used in Radar, LiDAR, ADAS , etc. 3) APHY - PHY& Link layer for MASS 4) PAL - Protocol adaption layer for MASS 5) App - Application Layer For MASS like CSI2,DSI2, I2C, GPIO ,Includes FUSA protocols like CSE, DSE… Read More »MIPI A-PHY & MASS – Revolutionizing Automotive Connectivity
Unveiling the Secrets to Proper Version Control, Seamless Data and Tool Integration, and Effective Collaboration
Overview Title: Unveiling the Secrets to Proper Version Control, Seamless Data Integration, and Effective Collaboration Date: Wednesday, August 23, 2023 Time: 10:00 AM Pacific Time Duration: 30 minutes (+15 minutes live Q/A) Join us on Wednesday, August 23rd, to learn how to master semiconductor design success as we unveil the secrets to proper version control, seamless data integration, and… Read More »Unveiling the Secrets to Proper Version Control, Seamless Data and Tool Integration, and Effective Collaboration
Optimize Test QoR & TTM with AI-Driven Technology
Continuously increasing semiconductor design sizes and complexity have resulted in increased test costs. Today’s competitive environment and critical market windows are pushing companies to adopt aggressive design schedules. The traditional method of manual iterations and fine-tuning test configurations to optimize test quality-of-results (QoR) is highly unpredictable and inefficient. Engineers can no longer rely on such… Read More »Optimize Test QoR & TTM with AI-Driven Technology
IP Lifecycle Management for Chiplet-Based SoCs
Chiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups, DoD projects, and academic research. Chiplet-based architectures bring their own set of challenges however, especially in the context of IP… Read More »IP Lifecycle Management for Chiplet-Based SoCs
Virtuoso Studio and Signoff Technology Day
Cadence Design Systems, Building 5 2655 Seely Avenue, San Jose, CA, United StatesJoin us at CadenceCONNECT™: Virtuoso Studio and Signoff Technology Day focusing on our latest technology within the new Cadence® Virtuoso® Studio. Date: Thursday, August 24, 2023 Time: 8:30am – 5:00pm Location: Cadence Design Systems, San Jose, CA | Building 5 Learn how the best analog tools just got better to help you keep pace with… Read More »Virtuoso Studio and Signoff Technology Day