Calendar of Events
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1 event,
EMC+SIPI 2023
EMC+SIPI 2023 leads the industry in providing state-of-the-art education on EMC and Signal Integrity and Power Integrity techniques. Don't miss out on this valuable opportunity to learn from and network with industry leaders and peers.
2 events,
Accelerate Coverage Closure with Synopsys VSO.ai
Accelerate Coverage Closure with Synopsys VSO.ai
70% of engineering time is spent verifying a design but it is largely a manual effort. As the industry faces ongoing engineering shortages companies are forced to make their engineering teams 10 times more productive at finding and isolating bugs per day. Increasing design complexities are also driving up the compute resources needed to verify… Read More »Accelerate Coverage Closure with Synopsys VSO.ai
2 events,
An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single "executable" specification. Appropriate Audience: ● Architects/RTL Designers ● Verification Engineers ● Pre-Silicon Validation Teams ● Post-Silicon Lab Bring-up Team Members ● Technical Writers ● Firmware Engineers ● Embedded Programmers Learn… Read More »An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
1 event,
ISPLED 2023
The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, system-level design and optimization, to system software and applications.
4 events,
Flash Memory Summit
Why Attend Flash Memory Summit? Flash Memory Summit (FMS) is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies, see the hottest products, and learn about what's happening and where the latest trends are heading.… Read More »Flash Memory Summit
Synopsys Static Verification SIG 2023
Synopsys Static Verification SIG 2023
Join us in-person on August 8th for the Synopsys Static Verification Special Interest Group (SIG) event. This event provides an opportunity for users, managers, and enthusiasts to stay connected with the latest innovations, techniques and methodologies. Attendees will hear about groundbreaking and successful applications and deployments of Synopsys VC SpyGlass RTL static signoff solution. Full agenda coming soon!
Deliver Next-gen Smartphones
Deliver Next-gen Smartphones
Stefan Rosinger, Senior Director, Product Management – Arm About this talk Join us for a look at how the latest Arm Cortex compute cluster launched as part of Arm's Total Compute Solution 2023 can help OEMs deliver next-level immersion, AI intelligence and security while promoting greater efficiency in their mobiles, laptops, home, and wearable devices.… Read More »Deliver Next-gen Smartphones
3 events,
CadenceLIVE India
CadenceLIVE India 2023 will be held on August 9-10 at the Radisson Blu Bengaluru Outer Ring Road. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users, developers, and industry experts to connect, share ideas, and inspire design creativity. Attendees have the opportunity to attend… Read More »CadenceLIVE India
Synopsys Formal Verification SIG 2023
Synopsys Formal Verification SIG 2023
Join us in-person on August 9th for the Synopsys Formal Verification SIG 2023 event. This event provides an opportunity for users, managers, and enthusiasts to stay connected with the latest innovations, techniques and methodologies. Attendees will hear about groundbreaking and successful applications and deployments of Synopsys VC Formal. Full agenda coming soon!
4 events,
Step-by-Step Guide for Your UCIe Design Verification
Step-by-Step Guide for Your UCIe Design Verification
As traditional Moore’s law scaling approaches its physical limits, the industry is moving towards multi-die solutions for higher electronics system densities. Multi-die designs present one way for engineers to pack more functionality into silicon chips and improve yield without affecting fabrication feasibility or project budgets. The Universal Chiplet Interconnect Express (UCIe) standard was introduced in… Read More »Step-by-Step Guide for Your UCIe Design Verification
Dealing with Inconclusive Formal Proofs
Dealing with Inconclusive Formal Proofs
Webinar Overview: Formal proofs of end-to-end properties can be a very valuable contribution to RTL sign-off and yet are often the most difficult to achieve. In this webinar Doulos Senior Member Technical Staff, Doug Smith will explore some practical ways of dealing with inconclusive formal proofs when using Jasper by Cadence . This includes the… Read More »Dealing with Inconclusive Formal Proofs
1 event,
UCIe: On-Package Chiplet Innovation Opportunities
UCIe: On-Package Chiplet Innovation Opportunities
High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure to meet the demands of today’s data centers, autonomous vehicles, etc. On-package interconnects are a critical component to deliver the power-efficient performance for this evolving landscape. Universal Chiplet Interconnect Express (UCIe), is an open industry standard with a fully specified stack… Read More »UCIe: On-Package Chiplet Innovation Opportunities
1 event,
Using Generative AI for ASIC Design
Using Generative AI for ASIC Design
Tools like ChatGPT can be used for a variety of purposes, including writing Verilog. Unfortunately, these models are not (yet) perfect, and the quality of the output varies heavily depending on how you use them. Just as models may "hallucinate" facts they are not certain about, they can also "hallucinate" buggy and non-functional Verilog. In… Read More »Using Generative AI for ASIC Design
3 events,
ERI 2.0 Summit
Watch as leaders from our government agencies, the Defense Industrial Base, and prestigious universities bring unique and indispensable perspectives on our domestic semiconductor industry, national and economic security, and future research directions. The Electronics Resurgence Initiative (ERI), DARPA’s response to national-level microelectronics concerns, is designed to ensure U.S. leadership in cross-functional, next-generation microelectronics research, development,… Read More »ERI 2.0 Summit
Advanced Analog Design Using S-parameters
Advanced Analog Design Using S-parameters
This webinar highlights the importance of S-parameters to IC design and how Semtech Corporation, a high-performance semiconductor, IoT systems and Cloud connectivity service provider, utilizes Siemens AFS XT simulation technology to accelerate Semtech’s design process without compromising on accuracy to develop differentiated analog solutions for wired and wireless applications. Two case studies of analog circuits… Read More »Advanced Analog Design Using S-parameters
MIPI A-PHY & MASS – Revolutionizing Automotive Connectivity
MIPI A-PHY & MASS – Revolutionizing Automotive Connectivity
1) Intro - MASS introduction 2) Usage - Full chip automotive systems from peripheral to processor and vice versa. E.g.Used in Radar, LiDAR, ADAS , etc. 3) APHY - PHY& Link layer for MASS 4) PAL - Protocol adaption layer for MASS 5) App - Application Layer For MASS like CSI2,DSI2, I2C, GPIO ,Includes FUSA protocols like CSE, DSE… Read More »MIPI A-PHY & MASS – Revolutionizing Automotive Connectivity
4 events,
Optimize Test QoR & TTM with AI-Driven Technology
Optimize Test QoR & TTM with AI-Driven Technology
Continuously increasing semiconductor design sizes and complexity have resulted in increased test costs. Today’s competitive environment and critical market windows are pushing companies to adopt aggressive design schedules. The traditional method of manual iterations and fine-tuning test configurations to optimize test quality-of-results (QoR) is highly unpredictable and inefficient. Engineers can no longer rely on such… Read More »Optimize Test QoR & TTM with AI-Driven Technology
Unveiling the Secrets to Proper Version Control, Seamless Data and Tool Integration, and Effective Collaboration
Unveiling the Secrets to Proper Version Control, Seamless Data and Tool Integration, and Effective Collaboration
Overview Title: Unveiling the Secrets to Proper Version Control, Seamless Data Integration, and Effective Collaboration Date: Wednesday, August 23, 2023 Time: 10:00 AM Pacific Time Duration: 30 minutes (+15 minutes live Q/A) Join us on Wednesday, August 23rd, to learn how to master semiconductor design success as we unveil the secrets to proper version control, seamless data integration, and… Read More »Unveiling the Secrets to Proper Version Control, Seamless Data and Tool Integration, and Effective Collaboration
IP Lifecycle Management for Chiplet-Based SoCs
IP Lifecycle Management for Chiplet-Based SoCs
Chiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups, DoD projects, and academic research. Chiplet-based architectures bring their own set of challenges however, especially in the context of IP… Read More »IP Lifecycle Management for Chiplet-Based SoCs
2 events,
Virtuoso Studio and Signoff Technology Day
Virtuoso Studio and Signoff Technology Day
Join us at CadenceCONNECT™: Virtuoso Studio and Signoff Technology Day focusing on our latest technology within the new Cadence® Virtuoso® Studio. Date: Thursday, August 24, 2023 Time: 8:30am – 5:00pm Location: Cadence Design Systems, San Jose, CA | Building 5 Learn how the best analog tools just got better to help you keep pace with… Read More »Virtuoso Studio and Signoff Technology Day
1 event,
Hot Chips 2023
Hot Chips 2023 (advance program) will be held as a hybrid conference with in-person attendance at Stanford University from August 27 to 29, 2023. Conference Format Hot Chips 2023 will be a hybrid conference. You may register to attend virtual or in-person. The conference venue is the Dinkelspiel Auditorium on the Stanford University Conference. Sunday… Read More »Hot Chips 2023
3 events,
GlobalFoundries Technology Summit 2023
Register now and join us at GlobalFoundries Technology Summit 2023! GF Technology Summit (GTS) 2023 is our worldwide, annual series of technology-focused events. GTS brings together leaders from the commercial, business and research worlds to understand the latest technology challenges and opportunities, and partner to create the most innovative applications and solutions. GTS 2023 Highlights This year's… Read More »GlobalFoundries Technology Summit 2023
High-Speed Channel Signal Integrity Optimization
High-Speed Channel Signal Integrity Optimization
Join our webinar as we share new optimization techniques to improve the efficiency and performance of your designs. The Optimality™ Explorer in the the Clarity™ 3D workbench allows users to navigate the design space with a panoramic view that can compensate for many years of engineering experience with an AI/ML-based optimization engine. During our webinar,… Read More »High-Speed Channel Signal Integrity Optimization
3 events,
UCIe-Based Chiplet Verification – from IP to SoC
UCIe-Based Chiplet Verification – from IP to SoC
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence,… Read More »UCIe-Based Chiplet Verification – from IP to SoC
Four Important Signal Integrity Principles Demonstrated with Virtual Prototypes
Four Important Signal Integrity Principles Demonstrated with Virtual Prototypes
Signal integrity encompasses all the problems that arise when interconnects are not electrically transparent. One difficulty in understanding signal integrity principles is that these effects can't be seen, felt, or heard. Visualizing the fields using 3D full wave simulations helps to build intuition immediately. While visualization is no substitute for understanding the electromagnetic principles at… Read More »Four Important Signal Integrity Principles Demonstrated with Virtual Prototypes
3 events,
Accelerating Mainstream Adoption of Multi-Die Systems
Accelerating Mainstream Adoption of Multi-Die Systems
Synopsys recently hosted a panel discussion with Ansys, Bosch, Intel, and Samsung to share their insights on the rapid adoption of multi-die systems. We invite you to the public broadcast of the panel where each company shares their view on the groundbreaking technology, what challenges lie ahead, and how companies can realize the promise of… Read More »Accelerating Mainstream Adoption of Multi-Die Systems
Advanced Testbench for a Complex DUT
Advanced Testbench for a Complex DUT
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more… Read More »Advanced Testbench for a Complex DUT
Advanced Testbench for a Complex DUT
Advanced Testbench for a Complex DUT
Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex… Read More »Advanced Testbench for a Complex DUT