-
AI Hardware & Edge AI Summit
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesThe combined AI Hardware & Edge AI Summit comprehensively covers the design and deployment of ML hardware and software infrastructure across the cloud-edge continuum. For Enterprise ML Experts: Attend a unique AI systems event that will give you both hardware and software tools and techniques for training, deploying, and serving machine learning – the program contains… AI Hardware & Edge AI Summit
-
NoC IP- Transforming Chip Communication
Webinar Agenda : Introduction to Mesh and Crossbar Architecture Cache Introduction Support for latest AMBA 5 Safety and security features as ASIL Standard. Port configurabilities Who Should Attend: Professionals working on development of NoC IP. People keen to know how NoC IP is shaping new era of chiplet communications Freshers in the field of VLSI… NoC IP- Transforming Chip Communication
-
SystemC Evolution Fika
The SystemC Evolution Fika is a series of online workshops to discuss the latest SystemC developments and applications. We refer to these workshops as fikas, to honor the fika tradition of sharing a coffee, slowing down a bit, and talking about things that we care about. Event information Date: 12 September 2023 Time: 16:00 - 18:00 CEST Location:… SystemC Evolution Fika
-
DVCon India 2023
Radisson Blu Outer King Road, Bengaluru, IndiaOn behalf of the DVCon India 2023 steering committee, it is my pleasure to welcome you all to the 8th edition of the Design and Verification Conference in India planned from 13- 14th September 2023 as an In-Person conference. We want to carry forward the momentum, excitement and the enthusiasm witnessed during last year’s edition into… DVCon India 2023
-
Verification Futures 2023 Austin
Austin Marriott South 4415 South Interstate 35 Frontage Road, Austin, TX, United StatesThe Verification Futures conferences is dedicated to discussing the challenges faced in hardware and software verification. To view the agenda for this event please visit the VF2023 Event Page. The full conference program includes 17 talks covering verification challenges and solutions, formal verification, RISC-V, System Verilog, UVM for AMS Verification, and VHDL Verification View the full conference… Verification Futures 2023 Austin
-
FPGAworld Conference 2023 – Copenhagen
DTU Science Park 2800 Kongens, Lyngby, DenmarkThe FPGAworld Conference is an international forum for researchers, engineers, teachers, students, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC-based products, educational & industrial cases, and more. Registration for attendees is free and includes 2*coffee, lunch and go-home drink.
-
ORConf 2023
Hochschule Munchen University of Applied Sciences Lothstr. 64, Munich, GermanyFOSSi Foundation are pleased to announce ORConf 2023 will be taking place in beautiful Munich, Germany on September, 15th to 17th, 2023. It will start Friday morning and Sunday is currently reserved for tutorials and workshops. ORConf is an annual conference for open source digital, semiconductor and embedded systems designers and users. Each year attendees… ORConf 2023
-
AutoSens Brussels 2023
Autoworld Museum 1000 Brussels, Brussels, BelgiumWe’re bringing AutoSens to Autoworld in Brussels once again to meet and shape the future of ADAS and AV. You can look forward to the freshest agenda of over 60 speakers across expert panels, technical case studies, and sessions covering 12 key themes. You will experience an exhibition full of demos from technology companies at… AutoSens Brussels 2023
-
Maximize Design Productivity using Vivado ML with SystemVerilog
Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to FPGA hardware designers. We explore the features of SystemVerilog that are useful for RTL synthesis using Vivado™ ML Editions from AMD, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.… Maximize Design Productivity using Vivado ML with SystemVerilog
-
QuantumATK V-2023.09 Release: Highlights of New and Enhanced Features
Join our FREE online event to learn about the new and enhanced features and performance improvements in the latest QuantumATK V-2023.09 product release. - Enhanced ease-of-use of training Machine-Learned FFs with new predefined Workflow Builder blocks and templates - New interactive Interfaces Builder for building multilayer structures - New Accelerated molecular dynamics method for crystallization… QuantumATK V-2023.09 Release: Highlights of New and Enhanced Features
-
Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A subsequent webcast will demonstrate custom ISA verification. The multiple ISA verification problem is solved by RISCV-DV with configurability for ISA… Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
-
UCIe-Based Chiplet Verification – from IP to SoC
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence,… UCIe-Based Chiplet Verification – from IP to SoC
12 events found.