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UCIe-Based Chiplet Verification – from IP to SoC

September 21, 2023 @ 11:00 am - 12:00 pm PDT

Cadence, September 21, 2023

Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence, the verification topologies of such designs have exponentially increased.

In this webinar, we will explore challenges and effective solutions to optimize effort and improve productivity in the verification using “Chiplet-like” reusable verification components. This caters to all possible topologies enabling continuous verification from IP to Subsystem and finally, at the system-level.


September 21, 2023
11:00 am - 12:00 pm PDT
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