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Verification Futures 2023 Austin
September 14, 2023 @ 8:00 am - 5:00 pm CDT
The Verification Futures conferences is dedicated to discussing the challenges faced in hardware and software verification.
To view the agenda for this event please visit the VF2023 Event Page.
The full conference program includes 17 talks covering verification challenges and solutions, formal verification, RISC-V, System Verilog, UVM for AMS Verification, and VHDL Verification
View the full conference agenda below.
| 08:30 | Arrival: Breakfast and Networking | Slides | Videos |
| 09:25 | Welcome: Mike Bartley, Tessolve Semiconductor Ltd | ||
| Keynote Speakers | |||
| 09:30 | Safety and Security challenges in hardware IP development
Vivek Vedula (Arm Ltd.) |
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| User Top Verification Challenges | |||
| 10:15 | Ericsson’s Challenges of IP Development and Verification for Products with a Long Shelf Life
Alex Duhovich (Ericsson) |
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| 10:30 | Engines, Logistics and AI
Bahadir Erimli (Cadence Design Systems) Platinum Sponsor |
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| 11:00 | Refreshments and Networking | ||
| Multi-Track Session (AM) | |||
| User Presentations | |||
| 11:30 | 10 years of Verification Challenges
Mike Bartley(Tessolve Semiconductor Ltd) |
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| 11:40 | RISCV CPU Verification – Opportunities and Challenges
Divyang Agrawal(Tenstorrent, Inc) |
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| 12:10 | Validation of Hybrid Architectures
Suneil Mohan(Intel Corporation) |
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| Track 2 – Training Session 1 | |||
| 11:30 | What Can Formal Do For Me?
Doug Smith (Doulos) Gold Sponsor |
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| Track 3 – UVM for AMS Verification | |||
| 11:30 | Renesas’s Submission to the UVM-(A)MS working group
Peter Grove, Steven Holloway (Renesas) |
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| 12:30 | Lunch and Networking | ||
| 13:30 | A Modern Fable: The Lost Art of Processor Verification
Larry Lapides (Imperas Software Ltd.) Platinum Sponsor |
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| 14:00 | Advanced RISC-V Verification Technique Learnings for SoC Validation
Adnan Hamid (Breker Verification Systems) Gold Sponsor |
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| 14:20 | Improve the Quality of the Testbenches using specialized PySlint solutions
Balram Naik Meghavath (Broadcom ltd.,) |
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| 14:40 | Verification by Documentation
Hemendra Talesara (Independent Board Member) |
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| 15:00 | Refreshments and Networking | ||
| Multi-Track Session (PM) | |||
| Track 1 – Latest topics in Verification | |||
| 15:30 | Leveraging AMS verification and DMS verification for efficiency and quality in Mixed-signal designs
Aditya Devarakonda (NXP Semiconductor) |
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| 15:50 | Sigmasense | ||
| 16:10 | Methodology focused testbench generation
Benjamin Delsol (UVMGen) |
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| Track 2 – Training Session 2 | |||
| 15:30 | Using Non-Determinism with Formal
Doug Smith(Doulos) Gold Sponsor |
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| Track 3 – VHDL Verification | |||
| 15:30 | OSVVM in a NutShell, VHDL’s #1 Verification Methodology
Jim Lewis (SynthWorks Design Inc) |
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| 16:30 | Event Closes |