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IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis
Cadence Design Systems, Building 5 2655 Seely Avenue, San Jose, CA, United StatesPower integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity. These changes and challenges are ushering in the IR2.0 era ― a new paradigm for power integrity design and analysis. As a… IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis
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RISC-V Summit US
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesEach day, thousands of engineers around the world collaborate and contribute to advance RISC-V, the open-standard instruction set architecture that is defining the future of open computing. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly, enjoy unprecedented design freedom, and substantially reduce the… RISC-V Summit US
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RISC-V 101
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe RISC-V Instruction Set Architecture (ISA) is the future of computing. As an open standard, RISC-V is accelerating innovation and enabling unprecedented design freedom across every computing application. You've seen the headlines and stories. Now, here's your chance to learn all about RISC-V and why it is being rapidly adopted by organizations of all size… RISC-V 101
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IESA AI Summit
Trident Hotel Hyderabad Hyderabad, IndiaExperience the unprecedented growth opportunities in the semiconductor and electronics industry, fueled by rapid advancements in Artificial Intelligence (AI). Embrace the paradigm shift from software-centric approaches to hardware-centric solutions, captivating emerging markets in the realm of AI. Witness the powerful convergence of breakthrough technologies like the Internet of Things (IoT) and AI, igniting a renaissance… IESA AI Summit
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Proactive Data Center Management with Insight Platform
The DataCenter Insight Platform is an enterprise software solution that simplifies data center capacity management by making it proactive, rather than reactive. The platform is a database of data center “digital twins”—virtual models reflecting the aggregate of an organization’s toolsets and add/move/change workflows. By bringing together data that is typically siloed and using predictive computational… Proactive Data Center Management with Insight Platform
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TSMC 2023 Taiwan OIP Ecosystem Forum
Ambassador Hotel Hsinchu 0F, No.188, Sec. 2, Zhonghua Rd., Hsinchu City, TaiwanLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile… TSMC 2023 Taiwan OIP Ecosystem Forum
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Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can behave, such as non-linear addressing, burst access mode, registers accessed through an embedded CPU, and quirky registers. It will cover the following topics: Using user-defined… Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
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CMOS Circuit Techniques for Wireline Transmitters Part I
Synopsys Webinar – Part I In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume. This volume of network traffic demands an increase… CMOS Circuit Techniques for Wireline Transmitters Part I
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CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
Google 237 Moffett Park Drive, Sunnyvale, CA, United StatesIP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side, the concept of package managers is widely used to build a product from many different sources, but chip designers often rely on ad-hoc solutions which tends to build up… CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
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Ways to run cocotb: makefiles, cocotb-test, or your custom setup
cocotb enables Python-based hardware verification, and it integrates into your simulator of choice, such as Aldec's Riviera-PRO and executes Python testbenches in that context. In this webinar, we will look at ways to invoke your simulator of choice in a way that also starts with cocotb. We will show ways to extend the setup to… Ways to run cocotb: makefiles, cocotb-test, or your custom setup
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Elevating Consumer Electronics Design Through Cloud-Based Simulation
Electronics design engineering teams are under incredible pressure to quickly deliver innovative new product designs to meet skyrocketing market demand. Sign up for this webinar to learn more about designing better consumer electronics products thanks to simulation in the cloud. About this Webinar Consumer electronic devices are part of our daily lives and include phones,… Elevating Consumer Electronics Design Through Cloud-Based Simulation
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Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace, Government, and Defense Systems
Join industry experts from aerospace, government, and defense as they discuss the complexities of 3D Heterogeneous Integration (3DHI), highlighting some of the technological, manufacturing, and economic complexities as well as security, reliability, and safety challenges. The panelists will also share their insights on chiplets and interface compatibility in addition to how DARPA’s NGMM (Next-Generation Microelectronics Manufacturing research… Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace, Government, and Defense Systems
12 events found.