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Automated Power Intent Management Pre-synthesis for Large SoC Designs
With increasing chip design complexity, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases, UPF creation and assembly are among the key capabilities to ease the implementation for complex… Automated Power Intent Management Pre-synthesis for Large SoC Designs
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Debugging SystemC with GDB
Webinar Overview: This webinar explores debugging SystemC code with basic tools, including issues and strategies to make improvements. A large portion of the webinar includes a demonstration of a small design. Topics include single-stepping without getting lost and obtaining information about SystemC simulation status. The session concludes with ideas on how to simplify debugging and… Debugging SystemC with GDB
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IEEE Rising Stars 2024
Tropicana Las Vegas 3801 S Las Vegas Blvd, Las Vegas, NV, United StatesThe IEEE Rising Stars Conference is designed to inform, excite, enthuse, and bring together the top engineering Young Professionals and Students around the world to network and be inspired by each other. The program includes Technical Innovation Talks, Professional Development, Workshops & Competitions, and Networking Opportunities with industry and peers. The conference gathers Technical Professionals who are experts in emerging technologies such as: Autonomous… IEEE Rising Stars 2024
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VLSID 2024
ITC Royal Bengal Kolkata, IndiaThe 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024) are being held at Kolkata, India, during January 6-10, 2024. VLSID 2024 is returning to the city after 8 years since 2016. This flagship conference is bringing worldwide industry leaders, Indian and international industry bodies, and academic researchers in a… VLSID 2024
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CES 2024
Las Vegas Covention and World Trade Center 3150 Paradise Rd, Las Vegas, NV, United StatesRegistration is now open for CES® 2024 — taking place Jan. 9-12, in Las Vegas. Flip the switch on global business opportunity with CES, where you can meet with partners, customers, media, investors, and policymakers from across the industry and the world all in one place. Don't miss your chance to be a part of the most powerful tech… CES 2024
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Speed Up Your Electronic Component Design with HPC
About this Webinar Electronic components design and their integration on PCBs involve complex simulations to predict EM fields and forces accurately. These simulations can be computationally intensive and time-consuming. High-Performance Computing (HPC) capability built into Ansys Maxwell core technology significantly accelerates the electronic component design process, enabling quick iteration, optimization, and validation. The ECAD capability… Speed Up Your Electronic Component Design with HPC
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RISC-V Day, Tokyo 2024 Winter
Ito International Research Center The University of Tokyo, Tokyo, JapanThe RISC-V Day Tokyo conference is the largest RISC-V event in Japan. The RISC-V Day Tokyo 2024 Winter conference will be held on Tuesday, January 16, 2024 from 9:00-17:00 JST (UTC+9) at the Ito International Research Center, The University of Tokyo. We will bring together excellent RISC-V-related technologies and products, as well as key people… RISC-V Day, Tokyo 2024 Winter
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PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture
“Right first time” is a goal we all aspire to, but how often does it really happen? Even when we follow layout rules as closely as possible, problems creep into the layout that cause issues during lab testing and result in costly, time-consuming respins. Join our expert presenter Todd Westerhoff in this LinkedIn Live… PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture
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Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
The heterogeneous integration of chips/chiplets has added significant complexity to the IC package design process, further compressing schedules for many design teams. Design teams must work more efficiently to meet quality and performance goals while maintaining schedule milestones. One way to improve efficiency is to shift signal and power integrity (SI/PI) analysis to earlier in… Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
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Verisium SimAI: Coverage Gaps Meet Their Match
Every project has some areas that seem impossible to cover. Various factors can cause these nearly impossible-to-hit coverage gaps, including technical complexity, lack of resources, and shifting requirements. In constrained random environments, simply running more random seeds may not always address these coverage gaps effectively. Overcoming these gaps requires creativity, persistence, and technical expertise. A… Verisium SimAI: Coverage Gaps Meet Their Match
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Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing. High speed interfaces like PCI Express® (PCIe®) 5.0 and 6.0 show promising… Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
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Introducing OrCAD X, Our Next-Generation PCB Layout Solution
Whether you’re a beginner or a seasoned engineer, this webinar is a must-watch for anyone in the electronic design space. Join us to discuss how you can accelerate your PCB design process with our new and improved OrCAD X layout environment. Learn how you can: Design with an intuitive UI Collaborate using design review and markup… Introducing OrCAD X, Our Next-Generation PCB Layout Solution
12 events found.