Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis

The heterogeneous integration of chips/chiplets has added significant complexity to the IC package design process, further compressing schedules for many design teams. Design teams must work more efficiently to meet quality and performance goals while maintaining schedule milestones.

One way to improve efficiency is to shift signal and power integrity (SI/PI) analysis to earlier in the design cycle. Instead of simply passing a completed design to SI/PI experts for inspection, design teams can now run in-design analysis (IDA) using intuitive graphical feedback to improve design quality. This change in process saves multiple design re-spins and produces high-performance, high-quality IC packages for even the most challenging schedules.

This webinar will educate IC package designers and their managers about Cadence in-design analysis software, part of the market-leading Cadence IC package design technology. It will showcase the latest updates to the guided, easy-to-use integrated design and analysis workflow that addresses the complexity of electrical challenges, reduces design iterations, and saves significant non-recurring engineering budget.