Automated Power Intent Management Pre-synthesis for Large SoC Designs

With increasing chip design complexity, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases, UPF creation and assembly are among the key capabilities to ease the implementation for complex SoC design projects and reach aggressive PPA requirements.

During this webinar the Defacto technical experts will be presenting a complete flow on how to strengthen UPF Management before synthesis based on the Defacto’s SoC Compiler design solution.

The Defacto-based UPF management design solution is a clear addon to mainstream low-power checking and implementation flows presynthesis. To manage UPF Defacto’s SoC Compiler is non-intrusive and used as an API to query, report and complete power intent information. Top level UPF can be easily built along with the RTL for design subsystems and SoC even if UPF views are not ready yet.

Last but not least, promoting UPF files to top level or demoting UPF files from top level to enable simulation and synthesis design tasks, is provided as a press button capability by keeping customization possibilities to fit user design flows.

Defacto’s power related capabilities are silicon proven and have been already successfully used on very large SoC design projects on many customer designs and the related flows will be presented during the webinar.

SPEAKERS

– Valentin Boyer: Product Manager

– Adrien Lecardonnel: Product Expert

– Chouki Aktouf: CTO