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Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
January 24 @ 8:00 am - 9:00 am PST
Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing. High speed interfaces like PCI Express® (PCIe®) 5.0 and 6.0 show promising results for compute intensive applications. Every successive generation of PCIe has doubled the bandwidth of the previous generation for e.g. PCIe 6.0, delivers double the bandwidth (64GT/s) of its predecessor i.e., PCIe 5.0 (32GT/s).
Come join us to learn:
1. How PCIe 6.0 can deliver such high data transfer rate of up to 64 GT/s per pin
2. Design considerations for PCIe 5.0 and 6.0 design IPs
3. Why verifying features such as Integrity and data encryption are critical.
4. Why industry leading PCIe design IPs companies trust us and how stay ahead of the curve
5. Reaching coverage closure faster through Compliance Testsuites
6. What’s next for PCIe.
We will also discuss how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs.
What You Will Learn:
- Overview of PCIe Verification
- Design and verification considerations when planning a new PCIe project specially around PCIe Gen5 or Gen6
- Unique features to Siemens Avery PCIe Verification IP and its Compliance Test Suite:
Testbench Creation and easy bring-up.
Run time Configurations.
Traffic Generation
Error Injection
Debug features
Various applications and use-cases
- Challenges involved in verifying advanced PCIe Generations
- Technical Demonstration
Who Should Attend:
- Design & Verification Engineers, Architects.
- Managers, Directors, Key Decision Makers.
What/Which Products are Covered:
- Verification IP, SV/UVM, PCIe, PCIe Compliance Test Suite, QuestaSim & Visualizer
Luis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe, CXL, NVMe, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe, CCIX, GENZ (Compliance Workgroup chair); and CXL, where he helped define Compliance Testing for CXL 2.0. At Siemens he is focused on the architecture of the UCIe Verification IP, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his master’s in computer science from National Taiwan University and is a fan of learning new languages.
Jalaj Gupta is Verification IP Product Engineer at Siemens EDA. Jalaj is responsible for providing support for PCIe and UCIe Avery Verification IPs. He has 10 years of experience working in simulation and emulation domain, from developing Verification IPs to transactor library development for Veloce to product engineering for leading edge Avery Verification IPs. He has worked on different protocols like USB, Ethernet, AMBA, I2C and PCIe. He is based in Austin, Texas.